CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences occur regionally. The good news is that if you are a registered attendee, you can access papers with your CDNLive! login. One paper I'd like to highlight is from the CDNLive! India conference in Bangalore back in October.
Manoj Sharma and Deepak Chauhan of Freescale India presented their experiences using C-to-Silicon to build an FPGA prototype of an Antenna Interface Controller, a digital component of an RF Interface chip. Like many of our high-level synthesis customers, they were looking to design at a higher level so that they can target different implementations. In their case it was for silicon testing and software development -- they wanted the flexibility to target different FPGA devices or emulation, and possibly an ASIC implementation if the quality of results were good enough. However unlike many of our high-level synthesis customers, their design was dominated by control logic. If you thought that high-level synthesis was only good for datapath-dominated designs, then you will be pleasantly surprised by their findings, which you can see here:
Now, this was not a huge complex design, but it highlights some key benefits of using C-to-Silicon:
The flexibility to use the same code to prototype on an FPGA, run an emulation, and build an ASIC
Fast turnaround of both design and verification
Comparable Quality of Results to hand-written RTL -- for a design dominated by control logic!
Easier re-use when targeting different requirements and process libraries in the future
If you are a registered CDNLive! attendee, I recommend you check it out. And if you are not, I recommend you register for a conference, there is a wealth of knowledge about the latest and greatest methodologies, techniques, and technologies.