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How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?

Comments(0)Filed under: System Design and Verification, C-to-Silicon Compiler, High-Level Synthesis, IP re-use, SystemC, TLM, C-to-Silcon, IP, reuse, re-use

During the planning phase for SoC designs, teams have to choose whether to "make or buy" the pieces of IP that will compose the SoC. The drivers of this decision are well-chronicled in a recent article by Ann Steffora Mutchler, appropriately titled "Make vs. Buy". I won't re-hash it here, though I might add one choice: reuse. Except for startups, most chip designs have IP internally that they can re-use from previous projects. The ability to re-use blocks is often lacking, as new process nodes or applications have different requirements, or perhaps the block was not designed for re-use in the first place. I wrote a post a couple months ago that detailed why designing with SystemC TLM enables more re-use. But that post did not venture into "what could this mean?"

Let's re-visit each piece of the "make vs. re-use vs. buy" decision and speculate on the impact on each of moving to higher-level abstraction design:

"Make". Designing and verifying at a higher-level of abstraction speeds the time-to-verified RTL. Plus it allows for broader micro-architecture exploration, meaning you have more room to make the IP more competitive. This makes the "make" option more attractive from a cost/risk point of view, provided that you have the expertise in-house to design the type of IP in question.

"Re-use". As I not-so-succinctly described in my blog post on this topic, designing IP with SystemC TLM will reduce the effort required to re-use that IP. So it makes the "re-use" option more attractive, provided that the IP is available from a previous project. But if the bar is lowered for the "Make" decision, and high-level synthesis makes IP easier to re-use, it's possible that over time, design teams will have more IP available to them from internal sources than they do today.

"Buy". As design teams can more easily "make" and "re-use", doesn't that mean there will be less need to "buy"? In some cases, yes. It goes back to whether you have the core competency to design this type of IP. If not, then you still buy it. If you do have the expertise, then you examine whether this particular IP block something that will differentiate your chip. If the answer to that is "yes", then it is likely you want to design your own differentiation.

But where there are clear market leaders -- for instance providers of processor cores, graphics cores, memory controllers, etc -- then you would still want to buy from them. Or if there's a particular standard or ecosystem requirement on your chip, then buying typically makes more sense. But in the rest of the cases where you do have the expertise, even though the IP does not differentiate your chip, designing it and re-using it across projects with high-level synthesis may lead to a long-term cost savings. It would depend on comparing how much it would cost to buy it versus the effort it would require to design it, and how much you could re-use it on future projects. High-level design, verification, and synthesis changes the inputs to that calculation.

So it seems like the growing adoption of TLM-driven design and verification is changing the dynamics of the "make vs. re-use vs. buy" decision. The question is, how radically? I'm not sure, but it seems that one very positive effect is that this can become more of a strategic business decision rather than an engineering resource constraint decision. That would be a great improvement from where we are today.

Jack Erickson

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