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edaForum: Evolving Devices from “All in One” to “One for All”

Comments(0)Filed under: debugging, Frank Schirrmeister, Intel, embedded software, Power Analysis, System Design & Verification, System Design and Verification, virtual platforms, EDA360, virtual prototypes, System Development Suite, one for all, Eul, hardware/software co-development, Shirrmeister, all in one, power, PCB, IMC, IC/package co-design, IP integration, edaForum

This week I had the pleasure to attend and to present at the 11th annual edaForum, held in Berlin, Germany. Coming back to my hometown and presenting at this conference was a real treat, even though the traffic was much worse than I remembered, mostly because on that day the Pope visited Berlin.

The edaForum kicked off with a fascinating keynote given by Prof. Dr. Hermann Eul, President of Intel Mobile Communications, IMC, the former Infineon division that is now part of Intel. Dr. Eul first noted how the mobile market exceeded previous volume predictions and how the predicted shift to the "All in One" device happened. He then outlined the challenges ahead - how those devices need to become "One for All" communications mechanisms as everything computes and connects.

Dr. Eul then noted his condition for giving the keynote speech - being allowed to express wishes. His seven wishes were mostly directed at the EDA and embedded software (ESW) industries, setting requirements for system design tools from IMC's perspective. It turned out that Dr. Eul's keynote was a perfect setup for my presentation later in the day, called "Blueprint for Transformation - How EDA is Changing to Support the New Development Paradigm."

But let me start at the beginning. Dr. Eul last had given a keynote at the edaForum back in 2007. He reviewed the tumultuous time since then - a big recession, the fastest recovery ever and now the potential of facing a recession again. Back in 2007 Dr. Eul made predictions about mobile phone shipments and was happy to report that in reality the market had actually grown faster, as shown in the following graph:

According to these forward looking predictions, we will reach shipments of about two billion devices in 2015. Dr. Eul commented that the existing 2G technologies will live longer than expected, 3G will still be the mainstream for the next couple of years, and new technologies like 4G/LTE are expected to grow slower than originally predicted.

Dr. Eul documented another prediction with a slide from his 2007 keynote, showing how phones would become the "All in One" devices.  Clearly this prediction has become true as well. So what is next? There is still room to grow in emerging countries, and as a result IMC is driving a dual focus on both high-end smart phones driven by apps and apps processors, and low entry phones for which high integration on chip is the biggest concern.

As a segue into his wish list of requirements, Dr. Eul described Intel's 2015 vision, in which data is shared securely across public and private clouds. In this vision Information Technology will be able to focus more on innovation than management, and - most importantly for communications technologies - services can be optimized as client aware, that is, based on the client's capabilities. In this continuum of devices we find "One for All" communications - all devices compute and connect, making decisions in technology irrelevant.

The framework for Dr. Eul's wish list was based on what he called a holistic design approach, in which technical and economic factors are all working together. His seven point wish list reads like this:

  • HW/SW co-development: Dr. Eul described a chip for which bring-up took three weeks as opposed to three months in the previous generation. Through efficient co-development, IMC was able to avoid being late and avoid wasting work, also relieving pressure on the HW/SW integration team, which has very precious know-how about fixing problems. Dr. Eul called for more HW/SW co-development automation, making it part of the design flow, and part of the process. At the end of this post I am including a nice before-after visual that Dr. Eul used during his presentation.
  • Virtual Platforms: These are definitely adopted in production and they help IMC to reduce software development cost and get to bring-up faster as described above. However, the translation from the transaction-level (TLM) to RTL is done manually, which introduces new errors from one phase to another. Dr. Eul called for automation here - requiring one model for the blocks feeding both into virtual prototyping and implementation, essentially driving the hardware implementation completely from the system-level.
  • System Robustness: Dr. Eul called for for real-time simulation of multipath scenarios before silicon is available. Multipath in this context refers to simulating the signal propagation. An urban environment is an example - the slide showed a picture of New York and various signal paths which can be taken. Current performance of virtual platforms is not enough. IMC would like to get speed-up of up to 10x for virtual prototypes at appropriate accuracy to run these type of simulations.
  • 3rd party IP integration: The current issue is that IP integration is completely RTL focused, and is missing IP views for other flows like software. Again, manual efforts to create these views are error prone. Citing a solution the EDA industry should provide, Dr. Eul suggested the development of formal IP property standards to integrate IP smoothly into all flows. Ideally, this would come with standardized formal description of properties, which can be formally proven as well.
  • System Power Optimization: Today, IMC defines power targets based on requirements, use cases, definition of hardware and software. If the hardware architecture fits, then a lot of time is spent based on software optimization at the end of the flow to avoid contract penalties if they miss targets. It would be nice if they would not have to invest as much effort during the last couple of months before market entry, "the six month of sweat, blood and tears." Dr. Eul admitted that there may be no obvious solution here, but he is envisioning a holistic approach to power optimization including methodologies and design flows, and infrastructure and EDA tools, as well as specific processes, project organization and management
  • Power Supply - ESD Planning: Power supply planning is a key factor for the electro-static discharge (ESD) robustness of the final product, but requires error prone planning due to high complexity and non formalized data. No chip is without ESD issues, but related errors can endanger customer acceptance and/or ramp up schedules. Here Dr. Eul called for formal and compatible formats for all aspects of the design from PCB to package to SoC to IP, and the actual implementation technology.
  • Chip Package Board Co-Design: Starting with the comment that a line in a chip or routed PCB doesn't know whether it should be an antenna or not, Dr. Eul gave a great example of the insufficient handling of an on-chip inductor within different design domains, i.e. package, PCB, chip and analog macros. The proposed solution isa transparent view through the domains, enabling efficient propagation and validation of design aspects.

Given that five of Dr. Eul's seven wishes were system-level and software-related, my later presentation fit very well and it echoed some of the proposed solutions. The solutions are engrained in the EDA360 vision. My presentation started from the market backdrop of the electronic value chain of systems enabled by semiconductors and made possible by IP, EDA and embedded software. With software determining the user experiences in most application domains, the development paradigms need to change - just like Dr. Eul had described by example of IMC as well.

My presentation then continued to show the cost of software, how it can delay production, how it plays a growing role in the interaction with the design chain, and how prototypes representing the hardware at various levels - virtual platforms, RTL, emulation, FPGA prototypes - offer solutions but none of them meet all user care-abouts.

I closed the presentation showing some of the requests for EDA to step up to the system-level, similar to Intel's Gadi Singer's DAC keynote and ITRS data. The EDA360 vision is very much in line with the requests made, and I detailed some steps we are taking in the System Realization space to address the requirements our customers are setting.

We are not quite addressing all needs yet, but we have made important steps in the area of connecting different prototype platforms for hybrid execution and software enablement, as well as using the same architectural intent for simulation (virtual platforms) and implementation (high-level synthesis).

Overall the edaForum event was a great experience, well worth the trip. IMC's keynote outlined a lot of the requirements I could later comment on ... so it is good to see that we are all working in the same direction to make system-level design a reality.

I am looking forward to your comments!

Frank Schirrmeister 

PS: And as promised, here is the before-after graph Dr. Eul used to illustrate HW/SW Integration issues.

 

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