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Virtual Flash Memory Gets Real

Comments(0)Filed under: ISX, Incisive Software Extensions, TLM, TLM 2.0, System Design and Verification, virtual platforms, Memory, virtual prototypes, IP, Virtual System Platform, flash memory, Flash Memory Summit

This week's Flash Memory summit will not only highlight the IP Cadence delivers, but will touch on innovative application of virtual prototype technology for Flash Memory firmware and system development. Developing complex memory controllers is challenging, and an increasing portion of the capability is delivered as firmware. Virtual prototypes of hardware for memory controllers, and the systems within which they operate, enable software to be developed months ahead of the first RTL for simulation or FPGA prototyping. In a fast paced consumer marketplace where memory speed and capacity are central to delivering the value of the device, time to market is everything.

The Cadence Virtual System Platform offers the ability to model hardware at the TLM abstraction to provide speed needed for rapid software development. In addition, Incisive Software Extensions provides advanced verification of software and systems using the Universal Verification Methodology to automate use case generation and explore corner cases of the system. These technologies will be discussed on a panel Wednesday morning, as well as in the Cadence booth.

A virtual prototype enables early development of software, as well as coarse grained architectural assessment. Certain types of system timing, throughput, performance, and system capacity measurements can be estimated, enabling teams to adjust design decisions early in the project. Detailed, accurate architectural analysis isn't possible until RTL is available and the system is fully functioning. The transition to RTL from TLM can be more easily achieved with the Cadence System Development Suite, which combines virtual prototypes with simulation, emulation, and FPGA prototyping as an open, connected, and scalable solution.


Fig. 1 -- Virtual prototype for a memory controller

 

The panel is Thursday @ 8:30am, session #302: "Nonvolatile Design Challenges and Methodologies" and the participants are:
  • Steven Shrader, Cadence
  • Mike Strickland, Altera
  • Steven Brown, Cadence
  • Aaron Olbrich, Pliant Technology

Come visit the Cadence booth to learn more!

Steve Brown

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