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System Development Suite - Connecting Software to Hardware Design and Verification

Comments(0)Filed under: System Design and Verification, verification, SystemC, TLM, ECO, software, C-to-Silcon, System Development Suite, Virtual System Platform, hardware

I've been at CDNLive! EMEA watching demos of the newly announced System Development suite, and it's mindblowing. I'm seeing good old ncsim running Android interactively on the Virtual System Platform. You open an app in the virtual Android interface and you can stop the software, or even the hardware model, at a breakpoint in ncsim. I'm seeing FPGA prototypes compiled at light speed with the Rapid Prototyping Platform. From a big picture perspective, Richard Goering's "The Story is the Continuum" really sums up the biggest deal here.

The language used to describe the early virtual prototype is SystemC TLM. Yes, I've been blogging about high-level synthesis in C-to-Silicon Compiler using SystemC TLM. Now we have a clear bridge between hardware and software. Keep in mind that even within TLM you can have different levels of detail. What you describe for the virtual prototype is essentially the algorithm, untimed, at a high level, so it can simulate really fast. You would refine that description for high-level synthesis, adding hardware architecture detail such as partitioning into threads and adding approximate timing for the system bus interfaces.

The hardware designers can start doing this with the same code that the architects use to create and verify the algorithm. It's just a refinement step. And there is still work for the hardware design team -- they have to specify the high-level constraints for synthesis and drive it toward an RTL implementation that will meet the spec of the target application. So this is a refinement process that is now connected all the way from early algorithm development and verification down into traditional implementation.

And verification is also connected. The virtual prototype becomes the golden reference model that simulation checks against when you're verifying each step of this refinement process. The really nice part is that each step can re-use the same verification environment and report back metrics.

Once enough verification has been run and implementation is underway, the RTL generated from C-to-Silicon high-level synthesis can be loaded onto the Rapid Prototyping Platform for even faster software development and verification. The entire process is connected! And if an issue is identified at this late point in the design cycle? You can fix the synthesizable TLM and C-to-Silicon can run in ECO mode, passing forward patch information to Conformal ECO, which can apply a patch at any point of implementation. Connected!

So this is an exciting announcement for many reasons -- and we are only just getting started.

Jack Erickson


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