Home > Community > Blogs > System Design and Verification > embedded software development requires open connected and scalalable virtual prototypes
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the System Design and Verification blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Building Open Virtual Platforms - Bridging the Gap of Model Availability

Comments(0)Filed under: architect, embedded software, virtual platform, SystemC, SystemC analysis, TLM, TLM 2.0, modeling, System Design and Verification, Models, TLM2, virtual prototypes, IP, architectural, multicore, multi-core, System Development Suite, Virtual System Platform, VSP

Virtual prototypes promise to enable early software development, shorten system bring-up time, and provide a resulting increase in revenue. One of the key barriers that project teams face when considering use of virtual prototypes is the "missing model syndrome" -- essentially the lack of adequate pre-built IP to assemble into the prototype, and the challenges of creating those models themselves. Some providers have created libraries of models, but without a standard language the models are proprietary and cannot be used in any other environment. The SystemC language (IEEE 1666) has added the important TLM 2.0 extensions, but writing models with TLM 2.0 requires practice and a methodology for reusability.

Cadence announced its new Virtual System Platform as part of the System Development Suite May 3. The Virtual System Platform enables pre-RTL software development, system functional verification, and system analysis and optimization before committing to a hardware micro-architecture. One of its key capabilities is its open modeling approach supporting processor models, and automating the creation of TLM 2.0 for interconnect and IP blocks. It incorporates high performance processor models from ARM, Imperas, and others that utilize SystemC TLM 2.0. What is new and valuable is the generation of TLM 2.0 code to speed the process of creating new virtual prototype models.

In order for models to be truly open and reusable, they must be written using SystemC TLM 2.0. The Virtual System Platform has TLM-aware capabilities that provides non-intrusive debugging and observability of the system behavior. Any TLM 1.0 or TLM 2.0 models will execute in the Virtual System Platform. It also comes with a TLM generation capability that uses a description of the pins and registers to generate all the TLM 2.0 interface code. As you can see from the process flow below, this code can be compiled and linked into a virtual prototype that can be used for early software compilation and simple register activity testing. Subsequently the function of each virtual prototype IP block can be added, in order to bring-up the operating system, such as Linux.

The TLM generation uses a textual or IP-XACT description of the interface pins and registers, and produces all the TLM 2.0 for the IP. This includes all the pin and register declarations, access functions, and C++ templates for implementing the functionality of the IP. Not only is this an open, standards based approach, but it provides an easy way to maintain the code as registers or pins are added, changed, or deleted. It also produces the header files needed for embedded software compilation, program files that test all the register read/write behavior, and the header files for integration with the rest of the virtual prototype.

There are other capabilities and benefits of the Virtual System Platform related to its connection to the rest of the System Development Suite, and its scalability for today's multi-core systems. Watch this space!

Steve Brown


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.