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Do You Have a DATE with Software? Cadence Does!

Comments(0)Filed under: System Design and Verification, RTL, virtual prototype, ip-xact, SoC, software, Virtual Platforms, IP, debug, DATE

How important is the software market to Cadence and as an element of the EDA360 vision? Important enough that Cadence is sponsoring several relevant sessions at the upcoming Design, Automation, and Test in Europe (DATE) conference in Grenoble, March 14-18, 2011. If you're anywhere near Grenoble in March, these are must-see events!

First there is a panel on the confluence of virtual platforms, the use of IP-XACT for assembly, and their potential for changing the RTL-based SoC design flow, on Tuesday, March 15, from 16:15-17:15.

ET02: "What is missing to enable global IP collection, assembly, and virtual platform distribution?"


The domains of RTL design, virtual platforms, high level synthesis, and IP assembly automation are converging to enhance the productivity and reliability of system level design methodology. A significant number of companies are creating RTL IP catalogs and leveraging assembly automation to rapidly produce incrementally innovative SoCs. Virtual platforms are enabling a growing practice pre-RTL software development. High level synthesis is increasing the productivity to create new RTL IP. The confluence of these forces is creating a plethora of opportunities, and presenting several challenges. This panel will explore and debate the priorities and benefits of these emerging trends and  discuss the following questions:

  • How far along are customers in creating internal virtual platform IP catalogs?
  • What are the challenges of organizing virtual platform and RTL IP catalogs?
  • How do IP-XACT and assembly tools help with this internal management problem?
  • Are companies starting to use 3rd party IP suppliers to provide virtual platform and RTL IP, as well as IP-XACT?
  • What are the challenges in defining IP catalog requirements to 3rd parties?
  • Are standards needed in addition to IP-XACT to enable freer IP creation and exchange?
Second, there will be a joint tutorial on a methodology for leveraging IP-XACT for virtual prototype IP creation and assembly, on Wednesday, March 16, from 13:30-16:30.

TS-1: Tool Seminar: "Unifying IP-XACT platform assembly with virtual platform modeling"


The goals for IP-XACT have expanded from RTL IP warehousing and easier SoC assembly. As virtual platform adoption has grown, the natural need arises to assemble TLM IP into a virtual platform, and refine it into the resulting RTL SoC. This tutorial will highlight the creation and assembly of SoCs starting from virtual platforms, key decisions to be taken, and potential issues to avoid.

And finally, there will be a panel discussion on trends in software verifcation and organizations, on Wednesday, March 16, from 1100-1230.

6.8 PANEL SESSION – Embedded Software Debug and Test

Today’s complexity of embedded software is steadily increasing.  The growing number of processors in a system and the increased communication and synchronization of all components requires scalable debug and test methods for each component as well as the system as a whole.  Considering today’s cost and time to market sensitivity, it is important to find and debug errors as early as possible and to increase the degree of test and debug automation to avoid quality losses.  These challenges are not only requiring new tools and methodologies but also organizational changes, since the hardware and software developer have to work closer together to achieve the necessary productivity and quality gain.  The panel will discuss new strategies in hardware and software development to make embedded software more reliable and easy to debug.

It should be a very interesting conference. Don't miss your DATE with Cadence!

Steve Brown


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