The dream of any marketer is a growing
demand for its product line. Let me start this blog by quoting the System
Realization (part of the Cadence EDA360 strategy) section from the transcript
of the recent (Q4) Cadence earnings call.
"In April (2010), we introduced the
Verification Computing Platform, enabling emulation, acceleration, and
simulation all on one single platform. Customers who are designing SoCs at 40nm
and below find this product necessary to meet the time-to-market and quality
targets. Demand for this product was exceptionally high in the fourth quarter,
the result of the expanded orders from existing customers and new customers who
used the platform to bring out some of this year's most extraordinary
Anytime the economy is recovering from
a recession, we see the demand for semiconductor devices growing, and with it
this increased demand for acceleration and emulation. Last year, we have seen an
even sharper increase in the demand for these products at Cadence. Why?
Let's talk about some of the market
of the new SoC devices are embedded. With the smart phone (both iPhone and
Android-based phones) and ARM-based design "Tsunami," the potential revenue
(produced by the semiconductor and the system companies) in terms of both upside
and risk is larger than ever. Overall, there is a reason why the market
capitalization of Google and Apple combined is above $520B, and ARM market
capitalization just hit today $14B.
new embedded device has more software than hardware and for the HW-dependent
software layers, you can't start software development until you have matured
hardware. HW/SW and embedded system integration is becoming the critical path in any system
hardware portion of new embedded devices is more complex and mostly includes
a recent discussion with one of our customers, he said: "In the past, during
the debug process, I could point into the specific line of software code which
was the root cause of the hardware failure. Today, when I have 12 cores in the
design with multiple operating systems, it is very difficult to find the root
cause for a particular failure manually. I need to rely on tools for automation
and even if I have it, it is a complex task".
used to be the key tool for block and SoC verification. In the new world, where
you have many external interfaces to your device, a lot of SW and a huge
complexity in integration, your simulation performance can't keep up with the
requirements. Unlike in the past, hardware-assisted verification is a must
growing business demand (which in many cases is pushed by us -- the end
customer) creates huge pressure to hit the shipment window on time.
Therefore, the demand for HW/SW
development platforms and high-performance simulation acceleration platforms
for verification acceleration is growing.
So why is it that the demand for other
platforms (such as FPGA-based prototyping and/or virtual prototyping) is not
growing at the same rate? I believe that overall, the demand for all HW/SW
platforms and SoC/system integration tools is growing. However, acceleration
and emulation still has unique value propositions:
larger percentage of designs are crossing the 64 million gate range. Emulation is still
the most convenient way and maybe the only way to port and validate such large
designs (hardware and software) at a cycle accurate level. Yes, it is true, if
you mostly need to test the SW independent layers and you do not particularly
care about cycle accuracy, there are other methods to do it. However, with the
hardware dependent layers, corner cases at the RTL/gate level are the ones that
eventually can delay your system delivery.
the ease-of-use improvement and the large number of available SpeedBridge
adapters, emulation bring-up is a task that can take now days for most designs.
Therefore if you have the majority of your design defined in RTL, this is the fastest
way to get to system validation.
new methodologies (OVM and UVM) are very efficient; however, they are running
out of steam as you get to the SoC and system level. SoC verification is not
scaling any more if you just use simulation. In parallel, the new standard
methodologies (combination of UVM acceleration and SCE-MI) made it much easier
to port designs in simulation and run them in acceleration. Moving forward, HVL-based
simulation acceleration could have a huge opportunity to grow.
the last 20 years, a lot of emphasis in emulation was put on debug, to
the point that today in many cases the debug in emulation is as simple (or
maybe more efficient) for large designs than in simulation.
Add on top of the above a new platform
from Cadence (Palladium XP, Verification Computing Platform) supporting
performance speed that has not seen in the emulation business for a long time,
hot-swap to and from the Incisive Enterprise Simulator, scalable capacity, very
fast turnaround time as a result of fast compile time, and low power
verification and analysis capabilities -- and this demand for acceleration and
emulation will not surprise you any more.