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On-Demand Webinar: TLM Design and High-Level Synthesis

Comments(0)Filed under: SystemC, RTL, TLM, System Design and Verification, system C, C to Silicon, webinars

In case you missed it last week, Mark Warren delivered a very informative webinar over at EETimes TechOnline, on migrating to Transaction-Level Model (TLM) design and using high-level Synthesis. Fortunately, this webinar was recorded and is available on-demand here:

Practical application of high-level synthesis in SoC designs

This 1-hour presentation covers the following topics, along with some good Q&A at the end:

  • The benefits of moving to TLM-driven design and verification
  • Cadence C-to-Silicon Compiler overview and usage
  • Creating synthesizable SystemC
  • Analyzing results and exploring your design
  • Tying this methodology together with production implementation

Please let us know what you think. If you like it, maybe we can convince Mark to do more of these!

Jack Erickson



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