The electronic industry is moving from hardware-defined products to software-defined and application-driven products. As a result, product differentiation shifts to software content while hardware platforms and their development processes increasingly become increasingly commodities. Time-to-market pressures and the trend toward software-defined product functionality make the traditional sequential process – SoC/System development followed by board and device development followed by software development – obsolete.
SoC/System development requires the integration of many components including main processors, application-specific processors, peripherals, memory, graphics and multiple layers of software where the components themselves include sub-systems and are developed by a diverse set of multi-tier suppliers. The heterogeneous operating principles of the components, their enormous, deeply sequential complexity, and complex HW/SW protocol stacks pose challenges to the system companies they have not encountered before. In addition, compared to the past, the systems and sub-systems must now be developed with a reduced workforce that is increasingly globalized across company and geographical boundaries.
Time-to-market is the number one challenge in the system development. System companies are under pressure to meet their market window and to reduce their overall design cycle. Currently, they spend 50% of their development time in HW-SW system integration and bring-up.
The key problem is debug. Once you find a problem in your design, you would like to be able to get visibility into the hardware and the software and quickly be able to find out the root cause of the problem, fix it, recompile and re-run the design again.
In his latest blog, Brian Bailey gave an excellent overview about the variety of use models of acceleration and emulation.
7 months ago, Cadence introduced the industry's vision, EDA 360, including System Realization. Within the System Realization domain, we have announced our new Verification Computing Platform -- Palladium XP. The first 7 month period was a home-run for Palladium XP at Cadence and a great success. Why is that?
- As mentioned above, system integration, validation, debug and bring-up are the key bottlenecks in the system development process. In the current semiconductor competitive environment, customers are pressured to get their product to the market early while meeting the functionality, quality and specifications. You can tape-out your silicon successfully -- however, if your software is not running correctly on top of your hardware, you can not ship the product.
- Acceleration/emulation is still the main method to validate your full design (HW/SW) especially for high complex designs.
The Cadence Verification Computing Platform is addressing many of the problems above with combined simulation, acceleration and emulation capabilities. To hear more from our customers, watch the following Videos: nVidia, Nethra Imaging.