Will you have the System Realization tools you need? Will you know how to apply them and not waste 6 months of your schedule? The Cadence System Realization webinars are here to help you succeed! They provide a unique view into the rapidly expanding System Realization domain, and detailed technical insight into adopting ESL methodology, modeling
virtual prototypes, debugging multi-core software, and high level
sequential logical equivalence checking (whew!). The September webinars were impressive in their scope from virtual prototyping, multi-core debugging, and equivalence checking.
Continuing in October the webinars begin with TSMC detailing TLM design and verification, then continue with ARM describing embedded software development and optimization, Cadence illuminating our ESL services offerings, and after Thanksgiving, TSMC focusing on high level synthesis.
These technical webinars are ideal for engineers and managers who have to deliver not only silicon but embedded software, and who want to learn about new areas of system and software design and verification, strategies for adoption, and the benefits of these solutions.
Participants can register here.
TSMC
Reference Flow 11 – ESL focus on TLM design and verification methodology – Oct
6, 10am PST
The
growing complexity of systems is impacting the ability to produce and verify
new IP to meet functional specifications as well as performance, power, and
area constraints. TSMC established a new ESL scope for their reference flow to
help customers more easily adopt methodology to increase productivity. Cadence
contributed to the ESL reference flow, a part of which was the TLM design and
verification methodology.
The
methodology focused on IP blocks and describes the creation and refinement of
high level models through to RTL (reusing high level models at the next
subsequent level of abstraction), and the verification methodology to apply
functional verification through those stages of refinement (reusing the test
bench applied to higher levels of abstraction at the next subsequent level of
abstraction) .
This
webinar will introduce the various levels of abstraction in the stages of
refinement, and the approach to architect an advanced UVM verification
environment to reuse through the entire flow. A key design concept
consideration addressed in the methodology is creating models that can be used
for virtual prototypes, high level synthesis, and functional verification. A
key verification concept in the methodology is the use of verification planning
and management to document and measure the function verified at each stage of
the design refinement, including RTL. Ashok Mehta, Sr. Engineering Manager,
TSMC, will open the webinar with an overview of TSMC RF11. Leonard Drucker,
Solution Deployment Director, Cadence, will then overview
technical details of the methodology.
Developing software for
ARM-based devices–
Oct 13, 10am PST
Software content in embedded designs is growing fast to meet
consumer demand for capability, integration, and mobility. Embedded
devices are being released to consumers at a faster rate and semiconductor
design times are shrinking, so software is becoming a significant aspect for
system design and verification. Creating application software rapidly,
debugging efficiently, optimizing performance and power, and completing
hardware/software co-verification is more complex than ever. In this
presentation you will learn about the latest solutions from ARM and Cadence for
ARM-based embedded and application software creation, debug, and functional
co-verification. Solutions include ARM Fast Models that enable early software
development and co-verification with Cadence Incisive SystemC simulation; the
ARM VSTREAM running with the Palladium XP Verification Computing Environment,
enabling accurate co-verification with ARM cores and RTL SoCs; and both solutions sharing the
widely used RealView Development Suite (RVDS) for software development.
System Realization Services from Cadence – Oct 20, 10am PST
The need for shorter time to market and optimized system
design is driving adoption of new system design methodologies using higher
abstraction. SystemC modeling for system analysis, high level synthesis, and
virtual platforms for early software development are the most common areas
customers are requesting help. This webinar will highlight project examples
that illustrate how customers are employing new methodology and technology for
system design and verification, and the benefits of using Cadence products. It
will also describe various ways that Cadence services uniquely enable customer
success and adoption of these new solutions.
TSMC Reference Flow 11 – ESL focus on High Level
Synthesis – Nov 3, 10am PST
High
level synthesis is one of the key motivators for higher productivity IP design
and verification. TSMC established a new ESL scope for their reference flow to
help customers more easily adopt methodology to increase productivity. Cadence
contributed to the ESL reference flow, a part of which is enabling adoption of
high level synthesis. The methodology focuses on creating high level models in
C, C++, or SystemC and using an interactive approach to understand the
resources and timing of the design.
This
webinar will introduce the concepts of modeling for high level synthesis, and a
repeatable approach to creating high quality of results (QoR)
RTL designs that meet area, timing, and power constraints. Ashok Mehta, Sr.
Engineering Manager, TSMC will open the webinar with an overview of TSMC RF11.
Mark Warren, AE Director, Cadence, will then overview the
technical details of the methodology.
Steve Brown