Home > Community > Blogs > System Design and Verification > c to silicon compiler 10 1 ease of use and rtl qor
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the System Design and Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

C-to-Silicon Compiler 10.1 - Ease Of Use And RTL QoR

Comments(0)Filed under: C-to-Silicon, TLM, CTOS, synthesis, hls

In the continuing effort to make high-level synthesis more viable to mainstream RTL designers, Cadence has released version 10.1 of the Cadence C-to-Silicon Compiler (CtoS).

This new release continues the recent trend towards overall ease-of-use and Quality of Results. The already popular CtoS GUI has been expanded to now allow quick exploration of all loops, function calls and arrays within the design. The expanded Control and Data Flow Graph viewer easily visualizes the control structure and flow of data through the design – all while being cross-linked to the Source viewer and all other windows in the CtoS GUI. The new Relaxed-latency mode lets CtoS automatically choose where to add states to the design, thus accelerating the process to lead designers to optimal results.

Integration is the other main theme in CtoS 10.1, which has tight links to Cadence Incisive verification, where simulations of the input SystemC, generated RTL, or fast behavioral models can be kicked off right from within the CtoS GUI. Incisive can now also read the CtoS database, and thus has all the links between the SystemC and the generated Verilog, so users can keep their focus on debugging the higher abstraction SystemC while actually running lower abstraction Verilog under the hood.

CtoS continues to have tight integration with the Encounter implementation flow to achieve predictable timing closure in logic synthesis, easy equivalency checks with Conformal LEC and a true top-down, patented ECO flow where a small change in the input SystemC results in a predictably small change in the generated RTL. CtoS also offers a compact patched netlist due to integration with Conformal ECO.

Please contact your local Cadence sales or Applications Engineering representative for more info.

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.