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System Realization activities at CDNLive! EMEA this week

Comments(0)Filed under: System Design and Verifcation, cdnLive! system realization

CDNLive! EMEA will be held in Munich again this year, and there’s lots of news about Cadence’ offerings to address the productivity gap in Systems Realization. Here are the System Realization activities, customer presentations, and Cadence presentations you may choose to attend:


Tuesday, May 4

13:30 - System Design & Verification Techtorial • Part 1: TLM-driven design and verification; model refinement for high-level synthesis • Part 2: System Level Low Power Design

 

Wednesday, May 5

8:40 - 9:20
Cadence Keynote
John Bruggeman, Cadence Chief Marketing Officer
The Way Forward: A Blueprint for Transformation

10:30 SDV01
Efficient scheduling of emulation workloads using LSF
Arm Holdings

10:30 AC01
Lead institution for Advanced SoC Verification Techniques: HyperTransport 3 – An Example
University of Heidelberg

11:00 SDV02
Bandwidth and throughput measure for systems and interconnects with Cadence Incisive® Verification IPs (VIPS)
STMicroelectronics

11:30 AC02
Simulate a microcontroller debug environment utilizing SystemVerilog DPI
Hochschule Regensburg

12:00 SDV04
Early integration of embedded software into the metric driven verification process
Cadence Design Systems

13:45 SDV05
Fast SoC Architecture Exploration Using Traffic Simulation Techniques
Arm Holdings

14:15 SDV06
Integration of C++ software with ISX for embedded software verification
Cadence Design Systems

15:15 Demo 1:
SW development and Virtual Prototyping using IES, ISX and Fast Models from ARM

16:15 Demo 2:
TLM-driven IP/subsystem design with HLS using C-to-Silicon Compiler

17:15 Demo 3:
Customer Case study: ensuring high-quality and easy integration of IPs using Palladium

18:15 Unveiling of the Palladium XP verification computing platform, Accelerating Time and Improving Quality of System Development

 

Thursday, May 6


8:45 SDV07
Co-Verification of an interrupt-based firmware for a complex control sub-system
EASii IC

9:15 SDV08
Managing Complex SoC Validation using emulation in conjunction with fault insertion
STMicroelectronics

9:45 SDV09
Cadence System Design & Verification Roadmap
Cadence Design Systems

11:15 SDV11
ESL, The Road to Glory, And Patches on The Way - Real Stories about Using ESL Design Methodology in Product Development
Global Unichip Corp

11:45 SDV12
Developing synthesizable IP modules from TLM 2.0 descriptions – A methodology case study
Cadence Design Systems

12:15 SVD13
Extending the value of traditional in-circuit emulators to software virtualization using fast SCE-MI transactions to ARM processors
Arm Holdings

12:45 SDV14
High Level Synthesis of the CHStone Benchmark Suite using Cadence® C-to-Silicon-Compiler
University of Tuebingen

 

Steve Brown

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