Let me start by sharing some recent blog activity showing competitors doing some admittedly admirable marketing work. Check it out.
They write well, gather some good data, etc. All "good stuff" to help customers like you make an "informed decision". In the spirit of sharing other "good stuff" with you, let me review just a couple of 2009 highlights of our successes in the ESL domain.
2009 was the year Cadence launch significant new system-level/ESL products - C-to-Silicon Compiler, a key component of our TLM-driven design & verification solution. One might say that 2009 was not exactly an "optimial economic environment" in which to launch new products. In spite of that, C-to-Silicon Compiler has done really well...I've never had a busier year in my 25-year career!
Our initial focus was on enabling more automated design creation, synthesis, and verification flows vs RTL. While this isn't what most people think of as ESL, customers have agreed it is necessary to be able to build designs more quickly, in addition to conceiving how they'll be built and meet specs. Cadence also offers HW/SW solutions that are integrated with the TLM-driven designs & verification flow (and more easily identified as being in the ESL domain). Both of these solutions enable customers to start Software development earlier, and get the design done earlier, with high quality.
Sounds like what others might claim, so I want to recap for you a few of the customer successes you may have missed this year. These customers are just the few who were able to take the time -- imaging asking your boss for time "away from getting work done" to write success stories for an EDA vendor. We all thank them for sharing.
PMC Sierra presented on their deploying an OVM based approach to early HW/SW co-verification (at CDNLive San Jose)
- Texas Instruments presenting their success applying C-to-Silicon Compiler (at CDNLive San Jose)
- ITRI and Micronas wrote about their C-to-Silicon Compiler successes on John Cooley's www.deepchip.com.
- Fujitsu and ITRI presented their success (at CDNLive Japan)
- The Renesas success story was published
We also delivered some new capabilities in our TLM design & verification solution, highlights of which are:
C-to-Silicon Compiler 9.3
Improved overall ease-of-use
- Integration with Incisive Enterprise Simulator (debugging, simulation launch) and with Calypto SLEC
- General quality of results (QoR) for both ASIC and FPGA flows
Incisive Enterprise Simulator 9.2
Improved overall ease-of-use of SystemC debugging (layout, probing, performance)
- TLM2 native debugging support (auto-recording and tracing)
- Integration with C-to-Silicon Compiler and SystemC source debugging of RTL simulations (!!)
- Fast Models from ARM supported for SystemC and RTL co-verification
Incisive Software Extensions 9.2
SimVision HW/SW debugging support for ARM, Greenhills, GNU, and Virage Logic SW compilers
A busy year!
And now, I leave 2009 behind to go on vacation. See you in 2010!