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Verification Productivity Is Holding Back Electronic System Level Development Advances

Comments(0)Filed under: System Design and Verification, ESL, TLM, functional verification

There is a controversy brewing in our industry, and I'm about to step into it boldly. I don't expect to end the controversy, since it is about the definition of a three letter acronym. And we all know how much the EDA industry likes to create and debate TLAs! The confusion makes it difficult for customers to decide if ESL is valuable. What's more, there seems to be a tendency to focus on the parts of ESL that are exciting, but not recognize what must be addressed first.

What does ESL stand for and what does it truly mean for customers? Most people agree that the acronym stands for Electronic System Level. The main motivator for this term was to get the industry to rise above the silicon, the transistor, the gate, the processe. The exciting word in the definition was "System", the first time that there was an attempt to focus broadly on what was being built instead of how it was being built.

Today Electronic System Level reads a bit anemic because it doesn't focus on the Software, which is widely recognized as the driver of trends and issues in system development. ESL has been around a while, though as recently as 2006 Cadence tried to redefine the term to mean Enterprise System Level. While the news of that announcement was relevant (testbench acceleration for system level simulations), it wasn't justified to change the definition of ESL. Can't blame us for trying though!

So what? We have ESL and everybody's happy, right? Nope. It turns out there are several meanings to the term ESL. There's architectural decomposition of a design into HW and SW. There's generation of code from markup languages. There's assembly of SoCs from connectivity definitions such as IP-XACT. There's virtual prototyping hardware architectural creation and analysis, in the context of software. There's virtual platforms for software development. There's high level synthesis from C/C++ into the RTL flow. There's hardware/software co-verification. And I'm sure there are more.

However, when you take an objective look at the use of ESL technologies, the ones that are enjoying a surge of adoption are those connected (integrated?) with the existing RTL-based design and verification flow. This is one reason why 2009 is bringing a surge in virtual prototyping interest and high level synthesis evaluations. SystemC and high level synthesis enable feed into the RTL flow. What's interesting though is that the design flow is not the driver, it's verification.

Customers are increasingly unable to create and verify designs using today's RTL flow - the biggest SoCs simply require too many people, servers, tool licenses, and calendar weeks. The cost and schedule are not in line with market opportunity and competitive pressures. High level synthesis is attractive for two big reasons: creating designs is faster, and it enables faster SystemC/TLM functional verification.

So while customers are interested in virtual prototyping and virtual software development platforms, these alone do not improve their ability to meet tighter market windows. They also must have a more productive design and verification methodology. TLM design and verification is the enabler of ESL. It is today's ESL solution.

Team ESL


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