Home > Community > Blogs > System Design and Verification > emulation is here to stay
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the System Design and Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Emulation Is Here To Stay

Comments(1)Filed under: System Design and Verification, Emulation

A recent blog by Brian Bailey covered the emulation war. I would like to correct some of the facts Brian has mentioned and also add my own comments.

First, Brian, you owe Cadence an apology :)  You forgot some of the emulation announcements from Cadence. You mentioned Nethra Imaging, AMD and Silicon Hive as the ones that were announced in the past year. You forgot the following announcements: Sharp, Netronome, ICT and the recent nVidia announcement about their Palladium usage at the Fermi project (see my blog about "this week Cadence earning call") - all these announced in 2009. If you look at the past year, you can add to this list also Comsys and ARM so depends on your definition, you should count Cadence emulation public announcements of 6-9 companies.

As far as the role of the emulation market, since the number of large and complex devices in the range of 50+M gates is increasing and there is a need to run these designs with high fidelity , I predict this market will grow. Similar to 2003, as we will get out of the recession, I expect the CAGR here will increase at the high side of a single digit or even double digit growth.

I agree with your assessment that beyond emulation and overall HW-assisted verification, there will be more designs that will start in SystemC or in general in high-level of abstraction. These could be either synthesize to RTL and ported to emulation using high-level synthesis tools or will be ported to virtual platforms if the accuracy level is not critical.

Overall with increased of HW and SW complexity and IP reuse, the budget for sub-system, SoC verification, validation and integration will grow and therefore all tools addressing this market will increase usage.

Ran Avinun

Comments(1)

By Brian Bailey on November 3, 2009
I bow before you in acknowledging my errors. I had searched the Cadence site for announcements, and listed all of the ones that I had found there, plus a web search, but I have to admit though that in the back of my mind I thought there were more.
I will see that the article is updated to include the ones that I missed.

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.