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Synopsys’ “Synphony” Announcement – Welcome to the Party!

Comments(0)Filed under: System Design and Verification, verification, ESL, RTL, TLMI’m glad Synopsys realized the world really IS moving to the next higher level of abstraction above RTL and now the party can really get started!

It’s great for RTL designers, for their companies, and the EDA industry. With the huge productivity boost that'll come from working at a higher level of abstraction, perhaps the semiconductor industry could enter a new golden-age. Until this year, customers have been intrigued with high-level synthesis, but cautious about whether it’s just a fad or here to stay (like Twitter! ;-) But with Synopsys jumping on the HLS bandwagon, now customers know that all the major EDA companies are committed to delivering design flows/methodologies starting above RTL, and can think seriously about migrating their engineers to a new “post-RTL” world.

That migration won’t be easy. If anything, what I've learned from talking with customers looking to adopt TLM-driven Design and Verification, is there are many critical factors to consider:

  • Applicability to many different types of designs and target technologies
  • Designer productivity, learning-curve, and quality of results
  • Ability to flexibly support design changes (to fix bugs, or accommodate spec-changes)

...and perhaps most importantly of all:

  • Verification productivity across the whole flow/project lifecycle, i.e. verifying as much as possible early, at the higher-level of abstraction, and mimizing RTL verification downstream.

With verification consuming 50-70% of a typical project's time/resources today,  Amdahl's Law dictates that in order to realize the productivity potential of working at a higher level of abstraction, addressing overall verification productivity has to be a top priority.

So I heartily encourage customers to do their homework, take a careful look at everyone's capabilities in this new space, and start asking the tough questions.

Steve Svoboda


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