Home > Community > Blogs > System Design and Verification > dac best user track poster visualizing debugging using transaction explorer in soc system verification
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the System Design and Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

DAC Best User Track: Visualizing Debugging Using Transaction Explorer in SoC System Verification

Comments(1)Filed under: System Design and Verification, Incisive, DAC, SoC, Marvel

One of the great things about DAC is the opportunity to meet new people and find out what kind of things they work on. This year I had the privilege of meeting Alicia Strang, a Verification Engineer, at Marvell Semiconductor. I first met Alicia when she was assigned as the moderator for the User Track presentation I made on Embedded System Device Driver Verification. During the course of the week we discussed different verification topics, and at the end of the week it was announced that Alicia's User Track Poster was given DAC Best User Track Poster Award Honorable Mention. The congratulations is currently on the front of the DAC website on the bottom right side.

The poster presents a great story of how Cadence users utilize Incisive to improve productivity. The poster discusses how to abstract debugging by providing higher level views using transactions that can be used to provide a better view before diving in and getting lost in the details. Abstract debugging is currently one of the most important topics in SoC verification and one of the best ways to improve productivity.

The slides from the poster are available now.

After DAC, I caught up with Alicia and asked her a few questions to share with readers on cadence.com

Alicia, tell us a little bit about what you do at Marvell

I define verification methodology and develop the verification environment for the system verification team in the enterprise storage SoC group. I am also responsible for the of hardware/software co-verification environment for our pre-silicon and post-silicon test.

What do you like about your job?

There are so many new things happing in the verification field. It is never a boring job because I learn new things everyday. There are so many new tools to play with too.

What do you find challenging about your job?

Learning curves: to verify a system I need to learn the system including all the protocols used by the system. To use the new tools and methodologies I need to overcome the learning curves.

What have you found that makes your job easier?

New technology and tools always help to make my job easier.

How did you become interested in debugging?

Debugging is the everyday life of every engineer. When we write RTL we need to debug RTL, when we write test bench we need to debug test bench. To make the debugging process easier is to make the engineer's life easier.

Anything else about DAC 2009 you would like to share?

It was a good opportunity to see what's new in the EDA industry. And I got to network with other verification engineers and find out what they are doing to solve similar problems they are having on their projects.

Thanks to Alicia for sharing a little about her work and congratulations to her and her co-author Robert Carden on the best poster award.

Jason Andrews

Comments(1)

By vmotel on September 18, 2009
Hi Jason,
I have read Alicia's poster with great interest (by the way: congratulations to Alicia and Robert for the award !), because my customers of STMicro have adopted a very similar approach, based on linked hierarchical transactions and TxE. We have presented that at CDNLive! EMEA 2009 : "Architectural analysis at transaction level with C++ TxE" (the presentation can be found on the CDNLive! website : go to www.cadence.com/.../proceedingssummary.aspx , enter your Cadence.com login or create one if you don't have any, then go to "VI. System Design & Verification" and open Session SD&V02)
Globally, ST's approach is in line with the "eagle view" considerations, but with a few differences which are highlighted in our presentation:
- transaction come from bus or interface activity, but they can also be used to represent firmware activity or system level synchronization
- as the monitors, and some of the models, are written in SystemC, the SCV api is used for transaction recording instead of direct sdi: ST found it has good advantages
- quantitative analysis is performed on the transactions, to provide metrics for microarchitecture analysis (it is not only debug)
- C++ (Run-Time) TxE is preferred for scalable batch analysis (up to millions of transactions)
Also, I noted at the end of the presentation that Alicia suggests "transaction color coding" as a possible enhancement. It is not widely known, but it is already possible with the tcl scripting commands of TxE ! The command is "set_attribute highlight color_name", after the "accept" command.
I can confirm that indeed, abstract debugging improves productivity. Transactions alone help, links between transactions are fundamental, TxE and coloring help too.
Best regards,
Vincent

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.