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Full System vs Sub-system Virtual Prototyping

Comments(0)Filed under: System Design and Verification, RTL, TLM, virtual prototype

There is a strong movement in the industry to move to create Virtual Prototypes of systems, prior to RTL coding. These Virtual Prototypes are being used for early software development and architectural analysis. Since there are typically many blocks in a design, the development of a Virtual Prototype can be unwieldy. While you might have a goal of creating one, you may be dazed at the number of components that need to be created or acquired (multiple CPU's, DSP's, MPEG engines, multiple memory sub-systems, DMA's, etc.). Companies are realizing that they can successfully achieve productivity gains y working with sub-systems instead of full systems. After all, this is how many high-level design and verification tasks are done today (ie sub-system simulation on emulators, sub-system c models created for reference models, etc.). But what is the difference between a sub-system and a full system?

A sub-system generally is a well defined entity in your design. There are CPU sub-systems, memory sub-systems, disk sub-systems, etc. This systems are very complex in their own right and usually contain some form of processing unit (CPU, DSP, micro-controller, etc.). Below is a table that suggests some characteristics of a a sub-system vs a full-system:


The first advantage to creating a sub-system is that there are a smaller number of blocks to create or acquire. Looking at the table, you can see there are other advantages. Typically minimum performance requirements are lower then a full system. That is because lower level software is being executed, meaning less instructions, allowing reasonable simulation speeds will lower performance. Secondly, you will probably model sub-systems that you are most concerned about, which are the ones that you are creating. Therefore most of the models will be created rather then acquired. If you are using a TLM Driven flow (in which TLM models are the golden source for synthesis), then the TLM models for the platform need to be created anyway. If you aren't, then you should look at the productivity that such a flow provides.

Full system Virtual Platforms provide the ability to exercise complete functionality of a system. Creating one can take time in acquiring models, porting operating systems, developing applications, and making sure simulations speeds are fast enough to be productive. Sub-systems Virtual Platforms require less effort to create (less blocks, reuse TLM Design models), address a smaller problem (sub-system programming or analysis), and are less demanding on performance.

Leonard Drucker


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