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1st Ever Virtual Platform Workshop Deemed a Success

Comments(1)Filed under: System Design and Verification, virtual platform, DAC 2009

Yesterday DAC hosted the first ever Virtual Platform Workshop, a full day dedicated to the topic. Everybody I talked to at the event was very happy to see a full day devoted to the topic. There was a lot to learn from each other. Grant Martin has already posted some comments on the event.

I participated in the lunch panel which served as the mealtime entertainment. The other panelists were:

  • Jose Corleto, Qualcomm
  • Simon Davidmann, Open Virtual Platforms
  • John Goodenough, ARM
  • Mark Burton, GreenSocs

I'll try to summarize the main points of each speaker. I'm probably missing some things from memory, but feel free to post clarifications as comments.

Jose: Virtual Platforms are key to shortening time to revenue for new devices. Software comes at the end of the process and schedule delays can result in $10 M per week of lost revenue. Shifting the schedule for parallel development improves time to revenue.

John: Helping customers get chips done sooner is important for ARM. Complexity is growing rapidly, and providing models for ARM IP for Virtual Platform usage is important.

Simon: Multicore debugging is the straw that will break the camel's back and force software engineers to do more work using Virtual Platforms so they can gain visibility and control to deliver multicore software. Providing familiar interfaces for software engineers, such as gdb and eclipse, are important.

Jason: Bugs in hardware dependent software are critical and we need to use better verification tools to stress the hardware-software boundary, not just manual testing. More automation to utilize the Virtual Platform for constrained random verification is important. High-level synthesis will connect the design process to the Virtual Platform.

Mark: SystemC is not the best technically, but has been very good as a standard to bring the community together, so continue to focus on standards and use SystemC. Models should be free from the IP vendor. Sometimes, host-code execution and virtualization can be used in the context of Virtual Platforms.

In the question and answer part we discussed some past challenges with Virtual Platforms and why it is sometimes difficult for software engineers to adopt them. Some challenges include:

  • Missing models
  • Takes too long to create the Virtual Platform
  • Software engineers not available at the right time, still working on previous project
  • Lack of verification culture because software is easy to change or patch

The panel ended with a chance to predict what will be different at DAC 2010 in the area of Virtual Platforms. Although nobody had any earth shattering predictions, Mark Johnstone from Freescale went out on a limb and said that High Level Synthesis will be so successful that the software engineers will be writing SystemC and become hardware engineers, and that hardware engineers will use the skills they have in understanding parallelism to be able to write software for multicore systems.

Thanks to everybody that attended.

Jason Andrews



By Gary Dare on July 31, 2009
Thanks, Jason, for your article.  I found Mark's comments to be very interesting ... and note that he describes what software engineers could do on one hand, hardware engineers on the other.  But what about both of them, together?  That points out a need for change in both process and organization.

I'm a former customer of Mentor's Seamless CVE and have used it for creating virtual prototypes.  That product has been around for a while, so people have been using it for a while ... if they have the right user profile.  It will be interesting to see if necessity will drive more users into such a profile (hw and sw team members working together, or coordinated by a program manager).

Disclaimers: as noted, I was a customer of Seamless CVE.  And then I was on that program during my initial period at Mentor Graphics, where I worked until recently.  But now, I'm of an open mind! (:

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