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Cadence System Design and Verification at DAC 2009

Comments(0)Filed under: System Design and Verification, ESL handoff, ARM, C-to-Silicon, SystemC, DAC, schedule

Traditionally in Cadence Marketing there were always two major events you really had to focus on: Sales Kick Off in the winter and the Design Automation Conference (DAC) in the summer. A lot has changed. Starting a few years ago, Cadence added a great deal more: webinars, seminars, segment-specific trade shows, and of course CDNLive! -- all to help you, our customers and users, stay up to date on the latest Cadence technology.Some voices in the past have accused Cadence of "ignoring" the annual DAC show. I can't comment about the past, but I can assure you that in 2009, DAC is important as ever. I have been in this industry for long time and attended many DAC shows and I can say for sure this year marks one of the most active DACs for Cadence that I can remember. Product Managers, AEs, even R&D people, have all been working round-the-clock to put together a line-up of demos, presentations, speaking opportunities, booths and other events, all so you can learn about the latest Cadence products and technologies.A very major highlight this year will be Cadence's new focus on the ESL/TLM space. In the past year we delivered a lot of new technologies there (and are announcing some new ones as well!). Recognizing the size and complexity of this space, as well as the huge opportunities for semiconductor, systems and EDA companies alike, Cadence is putting special focus on collaborating with partners (and even competitors) to bring an exciting line-up of events for you to enjoy.

Please join us for a variety of fun and educational events at the DAC show this 27-30 July at the Moscone Center in downtown San Francisco. Below is a summary of Cadence System Design and Verification activities at DAC. This list includes also DAC events with participation of Cadence employees.

Monday - July 27th

10:30am-11:00am Cadence Eco-system booth 4300 (North Hall) - Calypto

  • Calypto provides Sequential Logic Equivalency Checking (SLEC) capability as part of a TLM to RTL flow. Cadence C-to-Silicon Compiler creates automatic scripts for Calypto SLEC tool in order to compare the resulted RTL with the original SystemC TLM code. Calypto CTO Anmol Mathur will discuss how Calypto’s SLEC family provides comprehensive formal verification in flows using high-level synthesis tools such as C-to-Silicon Compiler.

5pm-5:30pm - Cadence Eco-system booth 4300 (North Hall) - Rohde & Schwarz

  • Rohde & Schwarz will present an early validation of wireless SoC using the CMW protocol tester. In this presentation, Rhode & Schwarz will feature their wideband tester and wireless protocol checking as part of Cadence ecosystem.

Tuesday - July 28th

9:30am-10am - Cadence ecosystem booth 4300 (North Hall) - Rohde & Schwarz - see above

10am-11am - Cadence eco-system booth 4300 (North Hall) - panel
Topic: What is the eco-system role in Virtual Platform/Prototyping?

With the increased percentage of Software content in electronic devices, there is an increasing demand for high-performance platforms for pre-silicon hardware/software verification and integration. Transaction-level models provide an excellent way to build such an environment. This panel will discuss the trends happening in this domain in terms of standardization and interoperability and the ecosystem required to support it from multiple points of view: the design tools provider, the processor IP provider, the verification manager, the system integrator and the SW developer.

Participants: Cadence, ARM, Virtutech and ST - I will moderate this panel.

11:30-1:30pm - Room 306-308 - System D&V luncheon
Topic: "Is SystemC/TLM D&V Ready to Replace RTL?

With a mix of "believes" and "skeptics", prepare for a stimulating debate on whether SystemC / TLM driven design has now evolved to a point where it is mounting a credible challenge to traditional RTL based design. Hear from the companies driving this evolution as they describe the productivity gains and real-world challenges they face in migrating their people, processes and technologies to this new approach.

Sponsors: Cadence, Forte & Calypto
Moderator: Freescale
including verification and high-level synthesis users

To register and get more information go to:

1pm-3pm - Exhibitor Forum Booth 4359 (North Hall) - Steve Svoboda, Cadence Design Systems
"System-Level Design and Chip Architecture Flow for Low-Power ICs"

4:30pm-6pm User Track: Room 132 - Jason Andrews, Architect, Cadence Design Systems
Design Flow for Embedded System Device Driver Development and Verification

Wednesday - July 29th.

Virtual Platform Workshop, room 301:

9:45am-10:45am - Jens Stellmacher, Cadence Design Systems
Modeling, Analysis and Refinement of Heterogeneous Interconnected Systems Using Virtual Platforms

11:11:30am - Cadence Ecosystem booth 4300 (North Hall) - Calypto - see above

12pm-2pm - Jason Andrews, Architect, Cadence Design Systems
Building and Using Virtual Platforms

Thursday - July 30th

11am-11:30am - Cadence Ecosystem booth 4300 (North Hall) - ITRI

ITRI (Industrial Technology Research Institute) uses Cadence's TLM-Driven design and verification flow (including C-to-Silicon and Incisive Enterprise Simulator) for their ARM-based design with AXI bus interface. In this presentation, ITRI will describe their flow, their use models and highlight results they have achieved to date.

4:30pm-6pm, room 131 - Jason Andrews, Architect, Cadence Design Systems
The Wild West: Conquest of Complex Hardware-dependent Software Design

Daily activities: July 27th to July 30th

Cadence Eco-system booth 4300 (North Hall)
When: Monday (July 27th) afternoon, Tuesday (July 28th) morning
Wednesday (July 29th) afternoon, Thursday (July 30th) morning

  • As part of the ARM pod of this booth, Cadence and ARM are going to demonstrate their mutual verification capabilities for ARM-based designs. You will be able to see three different demos including:
    • ARM-based HW/SW Environment with Dynamic Power Analysis
    • ARM fast models integrated into Incisive Enterprise Simulator
    • Metric-Driven Verification Flow for ARM’s AMBA Fabrics Using OVM

Cadence DAC suite - Booth 3751 (North Hall) - SystemC TLM-Driven Design and Verification Flow When: Multiple time slots every day

Using design examples, this session will showcase the full Cadence SystemC/TLM-driven flow for SoC front-end design and verification. The demo will highlight C-to-Silicon Compiler for micro-architecture exploration and RTL development and ncisive Enterprise Simulator. This demo will also highlight the critical roles of Cadence metric-driven verification techniques running on top of Open Verification Methodology (OVM) verification IP and design-planning tools working throughout the flow to ensure SoC quality and predictability. The flow will show the productivity benefits of IP/VIP reuse.

For more details and registration go to:

Cadence DAC suite - Booth 3751 (North Hall) - Reduce Power While Reducing risk
When: Multiple time slots every day

This session will show environment and methodology for design, verification, and implementation of digital and mixed-signal designs. It spans early system-level exploration through physical design and signoff, and leverages comprehensive exploration, estimation and analysis technology throughout including the ability to incorporate real-world hardware and software execution data. This demo will show you how the Cadence Low-Power Solution enables low power for all designs.

For more details and registration go to:

Ran Avinun


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