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Industry Standard SystemC is What Designers Want

Comments(0)Filed under: C-to-Silicon, SystemC, hls, System Design and Verification, ANSI-C

This past Monday saw not one HLS related announcement but two...this space is really heating-up!

Mentor’s Catapult announced support for control-logic design, and clock-gating (to reduce power) and Forte announced a new release with some minor new features. Today, I'll focus on Catapult, since their direction seems the most interesting in my view.

Mentor is promoting ANSI-C as their HLS input language with extensions into ANSI-C to create a "lightweight" (and Mentor proprietary) imitation of SystemC. To wit, consider the following statement in their press release:

"In the Catapult C Synthesis tool...a new synthesizable C++ construct, which allows designers to easily specify asynchronous data communication, allowing full control over concurrent hardware creation".

The industry standard SystemC class library (riding on top of ANSI C/C++) enabled this a long time ago.

But don't just take it just from me. ITRI (The “Bell Labs of Taiwan”, who do a lot of advanced chip designs) just told John Cooley/DeepChip this week:

"We like SystemC for high level synthesis since it includes everything in C++ and is the industry-standard way to describe hierarchy, concurrency, fixed-point arithmetic, and bus protocols -- more importantly, for designs with any significant control logic, the C-only-based tools simply do not work. We chose Cadence's C-to-Silicon tool because it supports SystemC."

“Feisty Forte” (my pet name for them, because they are the only tool I would consider even in the same league as C-to-Silicon, and I like their spirit!) has been saying the same thing for years as well:

"SystemC provides a standardized means of representing critical hardware concepts not available in pure ANSI-C solutions such as concurrency, bit accuracy, timing and hierarchy."

My point is that SystemC was expressly developed as an industry-standard extension to ANSI-C/C++ in order to solve the challenges associated with modeling and verifying hardware and software together. CtoS (and Forte) can both can accept ANSI-C/C++ input (in fact, most algorithmic code today is captured in ANSI-C/C++), but Catapult can’t accept SystemC. Native SystemC support is what you need to in order to have a truly “general purpose” high level synthesis tool.

Cadence, and to large extent, Forte, took the SystemC industry standard, and delivered tools that make it work (Cadence for verification as well as design).

If there's one lesson we've learned in the past several years is that customers want EDA vendors to follow industry-standards! That's why Cadence is committed to them. When CtoS was publicly announced in 2008 (after 3+ years of intensive engagements with early adopters) support for mixed control/datapath was the cornerstone of our value proposition to customers.

 

Steve Svoboda

P.S. CtoS has already had clock-gating available for nearly a year now (starting with the 8.4 release last Fall) and has 3 customers using it in production designs, routinely getting 95%+ gated flip-flops.

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