Home > Community > Blogs > System Design and Verification > system d amp v at cdnlive emea
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the System Design and Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

System D&V at CDNLive! EMEA

Comments(0)Filed under: System Design and Verification, Palladium, Virtutech, xtreme

CDNLive! EMEA has started today. I arrived here (Munich Germany) from SFO paying $340 for a round trip (record low for trip to Europe). Someone told me today the reason for this was that I have made my reservation at the same time the swine flu news were at their peak and with the decrease in demand for flights the tickets prices went down (go figure!). I like to start with one piece of good news. On my way to the airport the taxi driver told me that in the last month, his business started to recover. Mostly, my taxi driver input is a good indicator to the economic situation so maybe, we are at the start of a recovery (yeah!).

If you are a system architect, system engineer, verification engineer, SW developer or logic designer, I think, you have a lot to see at this show. The highlight of today was the system low-power techtorial. Through presentations and demonstrations and a lot of interactions with the audience, the seminar provided the audience a good understanding of the power issues and how these can be resolved with Cadence solution. One of the engineers in the audience told me it took him months to analyze the results we showed in the seminar you can get in minutes.

Tomorrow afternoon, we are going to have 3 exciting ESL demos - highly recommended!

  1. Next-generation high-level synthesis technology to enable TLM-driven design and verification flow.
  2. Integration of processor IP models with Cadence Incisive Enterprise Simulator
  3. Integration of Cadence Metric-Driven Verification using Incisive Software Extensions with Virtutech Simics virtual platform.

On Wednesday, we are going to have customer presentations (see below) at the System D&V column.

We are demonstrating our Xtreme and Palladium demos at the Cadence booth. See below the list:

  • Complete ARM-Based HW/SW Co-Verification Environment using Palladium III
  • Transaction-Based Acceleration for an Ethernet-Based Design using Xtreme III
  • System-Level Power Analysis with Palladium III / Dynamic Power Analysis
  • Emulation of Wireless SoCs with Palladium III

Overall, we have a great conference here.

Ran Avinun

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.