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System-level Low Power Techtorials/Workshops Off To A Great Start!

Comments(0)Filed under: System Design and Verification, ESL, C-to-Silicon, incyte, workshop, techtorial

Back in my 24 March blog I mentioned how Cadence was kicking off a major techtorial/workshop series across North America on low power chip design, using the newest Cadence tools at the ESL/System/Chip Architecture level.

Last week we concluded the first three events, all in California: Irvine, San Diego, and San Jose, with great attendance from big-name customers such as Cisco, Broadcom, ST, Qualcomm, and others.  The morning was mainly presentation and demos (with only one, very short marketing presentation...delivered by yours truly!) and the afternoon was dedicated entirely to hands-on workshops.

In the workshops, designers got to run InCyte and C-to-Silicon Compiler by themselves, on real designs...they were a hit!  Everyone was fully engaged, asked lots of questions, and although we planned each workshop to take about an hour, in many cases people went much longer, going well beyond the workshop "script", exploring other features in the tools.  This convinced me that hands-on workshops are perhaps the most effective way for engineers to try out new tools/methodologies and get a real sense for whether/how they could be applied on-the-job.  At each site, several engineers afterwards thanked me for inviting them and asked to please let them know whenever the similar workshop opportunities come up again.

If any folks reading this live in/near Austin TX, Arden Hills MN, Chelmsford MA, or Ottawa ON you might think about attending.  You can register at:  http://www.secure-register.net/cadence.php?product=8


Steve Svoboda



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