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Observations From the Embedded Systems Conference

Comments(0)Filed under: System Design and Verification, ESL, Embedded Systems Conference, RTL

Yes, there was another Embedded Systems Conference this year. Several "multi-year attendees" commented it was smaller. In the middle of it all was a theater where the stage provided easy viewing of various presentations, and a panel on Embedded and EDA markets converging. Executives from Cadence (Mike McNamara), Tensilica, Windriver, Synopsys, and CoWare joined moderator Ron Wilson for an interesting tussle about System Level Design. These guys know what's going on with System Design - they've been doing it their entire careers.

 

ESC_SV_4-1-09_3

For sport I spent my creative energy thinking about how a point made by a particular participant was posited to fit their individual interests rather than those of the industry. While I respect the achievements of every individual on that panel, my predisposition is to be suspect of their motives. Maybe someday I'll write a blog about that competitive analysis process.

There was a very cool floor demo: a robot that would compete with "all comers" in a game of airhockey! Not the most sophisticated, but I found myself entertained evaluating how this thing worked.

 

ESC_SV_4-1-09_9

 

The ~45 minute panel discussion was somewhat docile - I have to admit I was hoping for some good arguments. There were several debates, but mostly there were many, many interesting points made. The overall discussion broke down into two main themes: how do we need to look at System Design, and how should we tool for System Design.

One of the important topics mentioned during System Level Design was thenotion that system design has to handle optimizing the system for pre-architected IP (eg - processor cores), sw applications, and the "could be SW, could be HW" stuff in the middle. The panelists pointed at this topic from each of their respective positioned, but never summed it up in this totality. In fairness I know the "ESL industry" has been addressing this for some time. However, there are interesting issues about language to express such systems for analysis, optimization, and design. Those isseus were not debated, though Ron did ask about language.

A related topic that I will blog more on late is IP reuse. As more customers adopt system level design and verification, more IP will be created "at the transaction level". That IP needs to be designed for reuse - a concept that is vaguely defined in the ESL industry today. In fact, going back to the language point, there is actually a lot of disagreement, or misalignment, about TLM IP reuse. As I said, I'll blog more...

And finally, there was a shallow treatment of one of the more vexing questions for the industry. Who is going to become the ESL designer of the future? Our customers are not currently organized such that a natural candidate is obvious. The same issue existed when RTL emerged and become the language of choice. The role of an RTL designer grew from the designer community over time. RTL verification engineering was a role that came along later. Many of these engineers were groomed in college, not transitioned from hand-created digital logic engineers. So a similar question will need to be addressed: will the ESL design and verification engineers be groomed from today's RTL design and verification engineers? From the SW teams? From the architect teams? Or from today's college graduation classes?

 

Steve Brown

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