Home > Community > Blogs > System Design and Verification > c to silicon compiler is the only esl tool with eco capabilities
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the System Design and Verification blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

C-to-Silicon Compiler Is The Only ESL Tool With ECO Capabilities

Comments(0)Filed under: System Design and Verification, ESL, C-to-Silicon, RTL, CTOS, ECO

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to other ESL tools is its ability to make incremental changes to the generated RTL based on very small changes to the System C source code.

This capability, allows designers to make very small changes to the generated RTL and gate level netlists from a very small change to the input source code. Some of the changes that are supported by this approach are the following:

  1. Change of the sign of an input.
  2. Change inverting the logic level of a signal.
  3. Adding an extra condition to an “if then else” statement.
  4. Other minor changes to the input source code which reflect in minor changes in the generated RTL.

Without this capability, even a minor change to input source code, such as inverting a signal, might result in large differences between the original RTL and the RTL generated after the modification is done.

The user must notice that changes which imply major changes in the functionality of the generated RTL should not be treated with an ECO approach. Some changes in the System C code, such as changing the value of a template parameter, like the number of processors in an array processor, may result in a large difference in the generated RTL.


This Team ESL posting is provided by Dr. Sergio Ramirez, Sr Staff Product Engineer for the C-to-Silicon Compiler high level synthesis product. Product Engineer for the C-to-Silicon Compiler high level synthesis product.


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.