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Reflections on ESL: Where Are We and Where We Are Going

Comments(0)Filed under: System Design and Verification, ESL, C-to-Silicon, SystemC, RTL, EETimes, TLM

Many of the messages published by Gabe Moretti in his recent EETimes article resonate very well with Cadence strategy. 

Specifically:

  • Evolving standards are important with SystemC and TLM becoming the center of the ESL world
    • Cadence supports SystemC with its Incisive Enterprise Simulator and C-to-Silicon high-level synthesis
  • The need to connect the "ESL" world into the "RTL" world in order to migrate this (the ESL) world into the mainstream
    • Our philosophy is that any new IP which is being developed by design engineers should be developed at high-level of abstraction with the end in mind - i.e. this IP should be able to be automatically translated into RTL
  • The need for ESL synthesizers to address both control and datapath domains
    • Indeed, this is a key capability of Cadence C-to-Silicon Compiler
  • The concept of Model-Based Design (MBD) is based on continuous refinements of the design, progressing to less and less abstract representations, that are all automatically generated from the previous, more abstract, representation. C-to-Silicon is capable of extracting models in different levels of abstraction (Untimed, timed etc..) and producing models within different levels of abstraction (Approximately accurate, Cycle accurate and RTL). 

  • The evolution of platform-based design with IP re-use - the need to reduce development cost with the increased number of derivative IPs in the market create huge pressure on designers to re-use. The transition to a higher-level of abstraction can provide designers the following re-use benefits:

    • The same IP can be ported into multiple designs or multiple process nodes just by changing the constraints - the base design intent (algorithm) can stay the same. This approach can save weeks/months of manual RTL code development.

    • Multiple architectures can be created and assessed quickly

    • The design complexity can be reduced significantly

    • Design debug becomes much easier and few bugs can be found earlier

  • Key requirement for the above is ability to run ECO (Electrical Change Order) allows customers to easily identified the changed and incrementally synthesize the design without creating major change to their verification environment. The combination of C-to-Silicon ECO and Conformal ECO enables this flow.

Yes, the industry is making progress in the ESL domain and designers are starting to recognize it.

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