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SystemC TLM2 based Virtual Prototype Demo at DVCon

Comments(0)Filed under: System simulation and analysis, System Design and Verification, Hardware/software co-verification, Incisive, co-verification engineer, ISX, Coverage Driven Verification for Embedded Software, Jason Andrews, ESL, system validation/verification engineer, embedded SW engineer, architect, embedded software, QEMU, virtualization, virual platform, virtual protoype, virtual platform, Incisive Software Extensions, Co-verification link

DVCon 2009 promises much news about System level design and verification. With Open SystemC Initiative (OSCI) events such as the SystemC Users Group, and a TLM2 Modeling and Interoperability Tutorial, there's much to learn and contribute at the event.

Cadence will have a booth and one of the demos is titled:

"Virtual Prototyping with Metric Driven Verification and SystemC TLM2"

It will be available from 2-4pm on Tuesday the 24th, and 4-6:30pm on Wednesday the 25th.

So please stop by and see our technology!


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