I have the great honor of introducing a
wonderful paper on system level verification by Giles Hall. Giles is recognized
by all who know him as a verification expert, and was instrumental in the
founding of ISX. He worked tirelessly with numerous customers all over Europe
and the North America to demonstrate
techniques to improve the state of system level verification and explain how
the capabilities of ISX could help.
The paper outlines many of the
important challenges in system level verification including performance
challenges and how to perform verification when a DUT has become a mix of both
hardware and embedded software using a practical, easy to understand example.
Recently, Giles went on to become Chief
Engineer at ARC International and is now an ISX user. He
completed the paper as one of his last tasks for Cadence.
The publication of this paper
commemorates the 3 year anniversary of ISX development. It was exactly 3 years
ago today that a small group of us met in Israel under the direction of
Cadence Verification CTO Yoav Hollander to define and plan ISX. About
6 releases later we are still working to implement all of the ideas we
defined during the meeting, but we have made great progress in demonstrating
how to improve the state of system level verification and increase the quality
of embedded software used in today's complex SoC designs.
Congratulations and thank you to Giles
for writing the paper. My role was very small, mostly minor edits and
cleaning up the British English that I could not make sense of.
Enjoy Metric
Driven System Level Verification and as always feel free to share your
ideas on the topic.