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Power Aware Design Now at System Level

Comments(0)Filed under: System simulation and analysis, System Design and Verification, Acceleration, Hardware/software co-verification, Low power verification and analysis, Verification Acceleration, Simulation Acceleration, C-to-Silicon Compiler, debugging, ESL, system validation/verification engineer, embedded SW engineer, architect

Several years ago, I have purchased a cell phone with a 2 years contract from one of the major wireless service providers in the US. The battery lifetime between charges of this phone was terrible - 24 hours. The service provider promised me that there will be a firmware upgrade which will improve the battery charge time. 9 months later, I uploaded new firmware which allowed me to double the time between charges. These kind of issues are common within the electronic manufacturers community.

Why is it being discovered so late and by the end-user rather by the designer of the phone?

Why did it take 9 months for the software designers to fix it and provide a new firmware?

A year ago, I had a long discussion about power consumption with an engineer at a major semiconductor company in silicon valley. I have learned that this company is very conservative about power budget since it can not afford to fail. As a result, they were very conservative and had to use higher-cost packages in order to ensure working devices. The same engineer told me that more accurate power estimation will help his company to reduce the margin and lower the cost per device sold.

So, as you make your system power trade-offs, you need to make your assessment and the trade-off between being conservative (i.e. increase price per device) or being aggressive (which could cause you device failures or recalls).

In recent discussions with customers, I have found out that power estimation at the system-level is becoming more and more critical to design engineers.

Cadence has recently introduced two capabilities that help designers to estimate and explore power at the system-level.  

First, Cadence® InCyte Chip Estimator now offers low-power planning capabilities, including automatic creation of the Common Power Format. InCyte allows designers to perform accurate pre-RTL power estimation and to explore the impact of various low-power techniques. Within seconds, users can quantify the technical and economic impact of these techniques, at the pre-RTL stage in the design cycle. With a design specification as the primary input, users select parameters such as a target manufacturing process, what IP they are considering using within the device, performance targets and amounts of memory. In addition to estimating parameters such as die size, power consumption and cost, the system also enables side-by-side comparison of low-power techniques including multiple power domains, selective block power down, voltage scaling, clock scaling and more. Analysis can be completed in seconds and provide valuable feedback to assist in architectural what-if analysis, planning and feasibility assessments.

Second, Palladium® Dynamic Power Analysis helps to quickly identify the average and peak power consumption of SoC designs running with real software and real stimulus in various operational scenarios. In addition, Palladium Dynamic Power Analysis helps designers to compare power consumption among different design instances (i.e. finding “hot-spots” - which block/IP relatively consumes more/less power) and analysis of power consumption under specific working conditions. The capability is built on top of a Cadence HW emulation system and software solution that leverages the Cadence RTL Compiler power estimation engine and the SimVision waveform/power browser which is bundled with Palladium Dynamic Power Analysis.

If you want to read more information, read here.

I would also be interested to hear about your system-level power challenges and find out if these capabilities can potentially help you.

 

 

 

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