Home > Community > Blogs > System Design and Verification > cdnlive sj system design and verification don t miss it
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the System Design and Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

CDNLive SJ - system design and verification - don't miss it

Comments(0)Filed under: system validation/verification engineer, embedded SW engineer, power engineer, architect, low power

If you are a system validation/verification engineer, an architect, a power engineer or an embedded SW engineer, you should stop-by and visit us at CDNLive. See below some specific information on what you will be able to see in this domain: Hope to see you there.

- Ran

Day 1 - Monday - was very exciting with fully packed agenda including a full day of system design and verification techtorial with demos, customers and partners presentations. Thank you for those who attended and presented. Please share what you learned with the ones who did not have chance to be there and if you like us to improve our program for next show, write your comments below.

Day 2 - Tuesday (today)

         11am - low-power panel at Salon V on the second floor

         3:55pm - Track 1 Session 1FV5 – Using ISX to build a constrained random test environment from directed C-
                       based tests by NXP.

        4:45pm - Track 1 Session 1FV6 – An HDTV SoC Development Team’s first Experience with HW/SW Co-Verification
                       by Genesis Semiconductor

        5:45pm - The recent (July 14th) announced C-to-Silicon Compiler demo at the technology night

        6:15pm - Xtreme (with hot-swap) demo at the technology night

        7:30pm - The recent (Sep 8th) announced Palladium Dynamic Power Analysis demo at the technology night

        8pm - ARM-based HW/SW co-verification demo with a real design at the technology night

Day 3 - Wednesday

        10:30am - Track 2 Session 2FV7 – Maximizing the ROI of Palladium of Palladium HW to validate massively threaded
                        CMT processor - by Sun Microsystems

        11:20 - Track 2 - Transaction-based Acceleration        

        4:30pm - Cadence system design and verification overview and roadmap - main stage - 1R11

 

Day 4 - Thursday

       10am -  Track 1 Session 1FV12 – System-level verification of hard disk controller using Specman and ISX

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.