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Design space exploration

Comments(0)Filed under: System Design and Verification, high-level synthesis adoption, C-to-Silicon Compiler

In his latest blog post Space Exploration ... design is, Grant Martin said that ESL synthesis is an important tool in the overall design flow. Grant also mentioned that this capability opens new opportunities for the development of design space exploration tools that link into the various implementation flows from various vendors and for various alternatives and allow people to really explore space effectively.

For a single IP, Cadence C-to-Silicon Compiler can run multiple synthesis tasks for different set of constraints, save the results and allows the user to choose the best option. Another complimentary tool, InCyte Chip Estimator, allows you to select different combination of IPs and quickly estimate your IC size, power, performance, and cost.

You can easily combine these two methodologies together by taking different scenarios of your high-level synthesis results and run what-if analysis at the chip level that includes your re-usable IPs and the new IP/block that has just been created in SystemC. This capability allows you to explore different design options and trade-offs with different target vendors and IP combinations together with your own newly created IP without the need to run full layout for your chip.

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