RF Design - All Comments

Hi Shawn, Try usi ...

Tawna — Fri, 18 Nov 2011 19:21:04 GMT

Hi Shawn,

Try using the fourier component in analogLib. This component accurately calculates the number of harmonics you request with no requirement to set up any analysis options, except for possibly a tighter reltol and vabstol if your accuracy needs to be better than that produced by the defaults. While many things can be implemented, in this case, there just hasn’t been customer demand for this feature. I suggest you submit an enhancement request from your account at http://support.cadence.com so the request can be considered.

For some guidelines on using the fourier component, please see Solution 11251190

http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNu

mber=11251190

Best regards,

Tawna

I do not understand ...

Anonymous — Thu, 17 Nov 2011 00:51:28 GMT

I do not understand why these algorithms cannot be built into the algorithm. In other words, if one specified the "critical" signals in an analysis, it seems an FFT of the waveforms after the simulation is complete - or even better while it is running - would reveal the nature of the critical waveforms (I.e., number of harmonics). The simulation would be stopped and re-started if the number of harmonics was too small. This appears to be much more efficient (from a designer's perspective) as only a single simulation is submitted and the iterations are handled based on the waveforms of the critical nodes by the simulator itself.

Hi Stephan, One m ...

Tawna — Wed, 16 Nov 2011 19:29:05 GMT

Hi Stephan,

One more thing...Planning for environment and simulation is underway. At this point, we do not have direct replacement for measureLib. In the meantime, you may want to look at an alternate use model, that being ADE-XL multi-test environment. And as always, if there is a feature that you want but we do not yet have, please contact Cadence Customer Support and request that an Enhancement CCR (Cadence Change Request) be filed on your behalf.

Best regards,

Tawna

Hi Stephan, If y ...

Tawna — Wed, 16 Nov 2011 19:01:20 GMT

Hi Stephan,

If you are a Cadence Customer on Maintenance,

You may also want to look at Cadence Online Solution 11732744 "Guidelines for setting Pnoise/HBnoise sidebands to get accurate results"

support.cadence.com/.../cos

mber=11732744

or this blog posting:

Tip of the Week: Guidelines for getting accurate HB QPSS/QPNoise results (www.cadence.com/.../guidelines-for-getting-accurate-hb-qpss-qpnoise-results.aspx)

Best regards,

Tawna

finding Ft in cadence

finding Ft in cadence — Sat, 12 Nov 2011 14:34:40 GMT

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Hi Stephan, Pleas ...

Tawna — Fri, 11 Nov 2011 19:01:51 GMT

Hi Stephan,

Please contact Cadence Customer Support and request that a CCR be filed on this.

Best regards,

Tawna

Hi Stephan, you are ...

Tawna — Fri, 11 Nov 2011 18:37:14 GMT

Hi Stephan, you are absolutely correct. Rational interpolation is a reasonable choice if you have lumped elements. The rational model is not as robust and accurate as the convolution based model (linear or spline), particularly when the s-parameter data models distributed systems with long propagation delay, or the DUT is a multi-port system with the number of ports > 4.

best regards,

Tawna

Hi, is there a reaso ...

Anonymous — Fri, 11 Nov 2011 10:52:45 GMT

Hi, is there a reason why the measureLib is not part of Virtuoso IC61X anymore. What are the Cadence plans? Is there a workaround?

Hi, although not eve ...

Anonymous — Fri, 11 Nov 2011 10:49:50 GMT

Hi, although not everybody like it: If you know your s-parameter are presented well with a lumped element circuit (like package or LC filter, etc.), then 'rational' is a good choice!! Use not a too large 'order', usually it is best to use one more than the expected order. With rational you often get best transient behavior and extrapolation. Try to learn for your own: Make a little LC filter, simulated + save s2p file, then change testbench to include the s2p via nport and run e.g. a pulse step - and play with port settings. This way you can prepare for more complex cases.

Very useful. In some ...

Anonymous — Thu, 03 Nov 2011 08:53:49 GMT

Very useful. In some older docs it is stated that more oversampling than 2 is not recommended, but your suggestions are perfect.

Maybe tell us also on the impact of #harmonics and pnoise, etc.

Useful testbench to ...

Anonymous — Fri, 19 Aug 2011 22:00:44 GMT

Useful testbench to compare the different BSIM models

A good Figure of Merit to look at semiconductor process trade-offs if studying the fT and FMAX is to actually plot: fT x gm/Id as function of Vgs-Vt (overdrive) of selected processes. This will give you a plot and a good idea of optimizing the bias for the best performance in your design. This could be helpful when re-centering a migrated design.

Thank you very much ...

TheFunnyOne — Tue, 02 Aug 2011 15:54:02 GMT

Thank you very much for the information posted above. It helped me a lot in customizing my own viva environment. As a follow up, I want to describe the process that I used to initialize the viva background color. To be honest, I am not a big fan of black backgrounds as it is a little hard on my eyes. I usually prefer something softer like a dark gray so that the contrast between the axes and graph background is not too intrusive.

To set the default background of viva (not wavescan):

1) here is what I tried that did NOT work

a) First, I copied a default 'display.drf' to my cadence directory ~/cads/cadence

b) In the 'drDefineColor' section, I followed the syntax of other colors and created a custom color name called 'tfo1' and set the RGB value to 77,77,77

c) Then, I added a line in my .cdsenv file

viva.rectGraph background string "tfo1"

Everything loaded correctly but the background is still black! which is not what I wanted. Then, I changed the line to

viva.rectGraph background string "darkGray"

and the color changed to gray. This tells me that for some reason, viva does not recognize the custom color name that I set (perhaps due to loading order of the display.drf file compared to .cdsenv?? Your guess is probably better than mine.

I tried different color names listed above and the ones I've tried all works. But that still doesn't allow me to set the color that I wanted. Then it hit me that perhaps the color name can be replaced with HEX values instead.

2) So here is what I tired that did work

a) No need to modify the display.drf file.

b) Just add the following line to the .cdsenv file.

viva.rectGraph background string "#4D4D4D"

and that worked for me. 4Dh = 77d

Let me know if it works for you.

Hi Ahmad, Any of ...

Tawna — Mon, 27 Jun 2011 18:59:17 GMT

Hi Ahmad,

Any of the versions of SpectreRF on http://downloads.cadence.com (MMSIM 7.2 and MMSIM10.1 for example) support simulating switched capacitor circuits.

best regards,

Tawna

Hellow I need a sim ...

Anonymous — Tue, 21 Jun 2011 09:40:27 GMT

Hellow

I need a simulation version for switched capacitor circuit analysis

thank you

The BJT version of t ...

Anonymous — Sun, 29 May 2011 15:25:44 GMT

The BJT version of the test bench seems clear enough, but I fail to see how the MOS version will return a realistic result. It's true that MOS devices have Gate-Drain and Gate-Source capacitance, and those elements will pass a measurable signal at sufficiently high frequency. It's also true that latter-day MOS technology has significant Gate leakage, so there can be a realistic, non-zero, total Gate current value for any MOS device at sufficiently high frequency. Excess capacitance at the Gate terminal will introduce a bandwidth limit, but MOSFET short-circuit current gain is -not- established by Gate current. So a simulated ratio of Drain current to "Gate current" may return some kind of numeric result, and that result may not be entirely meaningless but it is not an accurate measure of MOSFET short-circuit current gain and thus not an accurate measure of MOSFET transition frequency. An accurate measure of transition frequency will require a different set of metrics, for MOSFETs.

Thank you for your e ...

Anonymous — Mon, 11 Apr 2011 22:52:50 GMT

Thank you for your explanation

If possible can you tell me the difference using MOSFET instead of BJT in figure 1?

thanks again

Its very good explan ...

SBALAND — Sat, 26 Feb 2011 16:43:36 GMT

Its very good explanation. Thank u.

Another good example ...

Frank Wiedmann — Wed, 08 Dec 2010 09:04:47 GMT

Another good example for simulation of switching regulators with pss/pac analysis can be found at www.edn.com/.../472586-Periodic_steady_state_and_small_signal_analyses_of_switching_regulators.php .

About S22 parameter of PA in transmitters?

About S22 parameter of PA in transmitters? — Thu, 02 Dec 2010 13:21:59 GMT

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Hi Mcromney, meas ...

Tawna — Tue, 09 Nov 2010 01:56:12 GMT

Hi Mcromney,

measureLib is in the IC5141cds hierarchy at path_to/tools/dfII/samples/artist/measureLib

If you cannot find it there, you may be using a very old version of IC software.

measureLib is not available in IC6.1.x.

best regards,

Tawna

Hi John, rfExampl ...

Tawna — Tue, 09 Nov 2010 01:52:00 GMT

Hi John,

rfExamples is in the IC5141 or IC614 hierarchy at:

path_to/tools/dfII/samples/artist/rfExamples

best regards,

Tawna

Hi Mcromney, The ...

Tawna — Tue, 09 Nov 2010 01:50:34 GMT

Hi Mcromney,

The measureLib library is not available in IC6.1.X. It is only in the IC 5.1.41 hierarchy at

path_to/tools/dfII/samples/artist/measureLib

If it is not in your IC5141 hierarchy, then you may be using a very old version of IC software. You need to be using at least USR6, I believe.

best regards,

Tawna

We do not have the m ...

Anonymous — Tue, 09 Nov 2010 00:44:16 GMT

We do not have the measureLib library available in the examples directory. I've searched all over for it. Is it a library that must be specifically requested?

Hi everyone How d ...

Anonymous — Mon, 01 Nov 2010 08:32:01 GMT

Hi everyone

How do you exactly access the rf examples in cadence?

I am unable to under ...

Anonymous — Wed, 08 Sep 2010 11:20:41 GMT

I am unable to understand how ft vs Ic plot is generated. How do you do a nested sweep of dc bias current and ac analysis to determine ft at each bias current?

Hi Rajesh, The PLL ...

Tawna — Fri, 20 Aug 2010 21:44:21 GMT

Hi Rajesh, The PLL workshop library requires specific paperwork to be completed by the customer (SPLA and SPLA Exhibit kit A I believe). You need to talk to your Cadence Salesperson to get the appropriate documents signed before the database can be released to you.

Hi Mehmet, If you have any issues with the artist states files in the workshops, please contact Cadence Customer Support (support.cadence.com) so that a CCR can be filed and the issue fixed.

best regards,

Tawna

The recorded webinar ...

Frank Wiedmann — Mon, 02 Aug 2010 08:17:06 GMT

The recorded webinar is available at www.cadence.com/.../event.aspx (registration required).

hi art did you ev ...

Anonymous — Mon, 19 Jul 2010 21:20:14 GMT

hi art

did you ever put up a test bench for fmax?

Hi: I am not able to ...

Anonymous — Wed, 14 Jul 2010 04:57:18 GMT

Hi: I am not able to find tar file related to PLL_workshop. PLL.pdf -- Noise Aware PLL design flow refers to this library. _ Thanx __ rajesh

Hey, thank you so mu ...

sidrai — Tue, 01 Jun 2010 10:29:24 GMT

Hey, thank you so much Tawna. An excellent post indeed.

This was indeed help ...

Anonymous — Fri, 28 May 2010 23:24:04 GMT

This was indeed helpful - but to plot beta vs f, I couldnt select the currents in the transistor teminals(it was reporting that the expression did not evaluate to an object to be plotted ), So I had to put a dummy voltage source and then select the currents from its nodes. Could you explain what was the reason

I can't wait for Par ...

gurusub — Tue, 25 May 2010 20:14:16 GMT

I can't wait for Part2

I am glad that Caden ...

Frank Wiedmann — Fri, 21 May 2010 09:14:10 GMT

I am glad that Cadence is finally addressing this subject (see my earlier comments at www.cadence.com/.../spectre-rf-by-any-other-name.aspx for some possible applications).

Great post. Like And ...

Anonymous — Fri, 30 Apr 2010 08:32:50 GMT

Great post. Like Andy1959 said, 'nice article. Clear concise, and to the point."

We, at Pinter Electronics Consultants, write similar content.

Check it out: www.pinterec.ca/.../blog

Hi Art, Could you ...

bVenu — Thu, 29 Apr 2010 14:17:27 GMT

Hi Art,

Could you possibly put up a test bench to simulate the Fmax of a transistor too?

Thanks

Venu

I can not the find t ...

Anonymous — Thu, 22 Apr 2010 11:57:08 GMT

I can not the find the .artist states in the tutorials. Did you guys forget to put in the folders?

Hi Sameer, This i ...

Tawna — Tue, 23 Mar 2010 09:06:41 GMT

Hi Sameer,

This is described in more detail in support.cadence.com solution 11575904:

support.cadence.com/.../cos

What is the difference between hb/hbac/hbnoise and the harmonic balance Q/PSS Q/PAC, Q/Pnoise ?

A brief summary of the solution:

In mmsim 7.1, we introduced new analyses: hb, hbac, and hbnoise. We recommend using these analyses in MMSIM 7.1 and onward. The analyses are essentially the same as the old harmonic balance Q/PSS and small signal analyses, but the hb/hbac/hbnoise GUIs are easier and more intuitive to use.

A good way to get started using the new analyses is to go through the RF Workshops located in the hierarchy at mmsim_hierarchy/tools/spectre/examples/SpectreRF_workshop/rfworkshop_hb.tar.gz

Can you explain if d ...

Anonymous — Tue, 23 Mar 2010 08:05:33 GMT

Can you explain if doing (a) hb analysis or, (b) QPSS analysis with hb engine one and the same thing? If so why there are two options?

Nice article. Clear ...

Andy1959 — Sat, 30 Jan 2010 11:15:07 GMT

Nice article. Clear concise, and to the point. A nonlinear example like a mixer or a sigma delta would also be very useful.

The application note ...

Tawna — Wed, 13 Jan 2010 09:51:08 GMT

The application note "Using the nport in Spectre and SpectreRF Simulations" has been updated for MMSIM 7.2 and IC 6.1.4. The application note illustrates how to use the nport component from the analogLib library in Spectre and SpectreRF simulations within the Virtuoso Analog Design Environment. You may access the appNote in the Design Topics section at www.support.cadence.com .

best regards,

Tawna

An application note ...

MarkSummers — Thu, 07 Jan 2010 06:39:19 GMT

An application note would a couple of basic examples would work well. A methodology that works for both switched cap and continuous time implementations would be very nice. Longer term a measurement test box may be the way to go. However having a good document as a reference to refer too is always a good thing. Hope this helps.

Mark, The r ...

Anonymous — Sun, 03 Jan 2010 05:59:18 GMT

Mark,

The request is has come up often recently. As the tools have advanced, it is difficult for designers to know when to use which technology for what problem. It is definitely something that we need to do more systematically. One question for you as a user, how would you like to see the guidelines provided: Published as application notes? As measurement testboxes? ...?

Can somebody give an ...

Anonymous — Thu, 31 Dec 2009 09:33:53 GMT

Can somebody give an overview of all syntax to customize viva?

Good post. Anything ...

MarkSummers — Sat, 19 Dec 2009 16:39:21 GMT

Good post. Anything that reduces sim time and allows things like corners and montecarlo is good. In paticular the non-linear topic will be interesting. Switched cap circuits take a while for transient simulations and improving these will help greatly. In particular sigma-delta designs would greatly benefit. I have seen some documents on how to check noise for sigma-delta ADC's with spectre-RF, however I have never been able to get accurate results. A comprehensive guide on noise and distortion simulations with sprectre-RF for these type of circuits would be of great benefit.

Hi RizwanAhmed, h ...

Anonymous — Mon, 16 Nov 2009 19:01:07 GMT

Hi RizwanAhmed,

http://support.cadence.com solution 11571722 may be what you are looking for:

Guidelines for simulating frequency dividers in spectreRF

best regards,

Tawna

Is there a step by s ...

RizwanAhmed — Thu, 05 Nov 2009 21:53:06 GMT

Is there a step by step tutorial about "how to simulate divde-by-2" ?

I have not run this ...

BunnyMan — Sun, 18 Oct 2009 17:52:57 GMT

I have not run this module, but from what I've read here, I agree with Kevin’s comments in that as much documentation as possible should remain on the schematic. This would make it easier to review and update both the design & test attributes together. I would also like to see the program read in the variables. Then, allow active test changes and document the final test parameters if any. Indeed, this is a great start (keep going!). I look forward to seeing any future updates.

A very good example ...

Frank Wiedmann — Thu, 08 Oct 2009 08:42:09 GMT

A very good example that shows how useful pstb analysis is for simulating the stability of DC/DC converters can be found at www.cadence.com/.../CD12_WerthT_iasrwth.pdf .

Hi Shail, I'm not ...

Anonymous — Mon, 21 Sep 2009 17:56:34 GMT

Hi Shail, I'm not sure what you mean by "wasn't able to find a download link to spectreRF". If you want to download the software, you go to downloads.cadence.com and download MMSIM 7.1 (for example). SpectreRF is included in the MMSIM stream.

best regards,

Tawna

hi all well i wasnt ...

Anonymous — Sat, 19 Sep 2009 02:13:57 GMT

hi all well i wasnt able to find a download link fo spectreRF can u plz send me the link or post it here...

thanks

shail