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Periodic Steady-State Analysis for DC-to-DC Converters

By Arthur Schaldenbrand on June 30, 2009Comments(5)Filed under: DAC, DC-to-DC converters, PSS, RF design, SFDR, shooting newton, Spectre RF, THD

In "Spectre RF by any other name ...", a non-RF application for Spectre RF's periodic steady-state analysis was introduced. An example of using periodic steady-state analysis [PSS] to simulate the dynamic performance: THD and SFDR, of a switched-current Digital-to-Analog Converter [DAC] was presented. In this append, we will look at using periodic steady-state analysis for another non-RF application, switching regulator simulation. Switching regulators are the core of switched-mode power supplies [SMPS] and are interesting because they are used in most power supplies, including the high efficiency power supplies required mobile applications.

Let's begin by considering a simple switching regulator design, a buck-down converter for converting from 12V to 5V, shown in Figure 1. The design is a voltage-mode, continuous conduction mode switching regulator. The control block: reference voltage generator, error amplifier and compensation, drives a pulse-width modulator: ramp generator, comparator, and switch. The output of the switch is filtered by an LC tank and feedback to the control block. The duty cycle of the pulse-width modulator determines the output voltage of the regulator. The inductor and capacitor non-idealities [self-resonance frequency, ESR, ...] are modeled but not shown. Finally an EMI filter has been included in the design.

 

Picture1

Figure 1: Buck-Down Converter schematic

 

First, let's look at the dynamic response of the regulator. After settling the start-up transient, the regulator operates at the frequency of the ramp generator. When operating at steady-state, the dc level is 5.002V and there is ripple on the regulated output voltage, ~+/-7mV. The transient response of the regulator is shown in figure 2.

 

Picture2a

 

Picture2b

Figure 2: Buck-Down Converter transient response

 

While transient analysis can be used to verify the overall performance of the circuit, it is difficult to analyze the circuit's performance in the time domain using transient analysis, for example, consider the challenge of trying to simulate the phase margin and gain margin of the control loop. Ideally we would like to be able to use simulation to improve the buck-down converter design in the same way that using ac, noise, stability analysis can be used for design of linear circuits. However, linear analysis can not be directly applied to switching regulator designs so we need to find a new methodology for analyzing the switching regulator. Since the switching regulator has a periodic steady-state, we will apply the periodic steady-state analysis technology in Spectre RF. In this case, a source is used to generate the ramp so driven periodic steady-state analysis is used. The complete setup for PSS analysis is shown in Figure 3.

 

Picture3

Figure SEQ 3: PSS Analysis setup

 

Since a switching regulator has fast changing time domain waveforms, the Shooting Newton [time domain] periodic steady-state engine was selected. If the Harmonic Balance engine is used, then a large number of tones would need to be selected in order to correctly represent the voltage at the output of the comparator and the switch output since these waveforms are nearly square waves. In this case, the stabilization time [tstab] is equal to the transient simulation time. In practice, a shorter stabilization time would be used to reduce simulation time. Allowing the circuit to settle to close to steady-state will help convergence. For this test example using a tstab of 2-3us should be sufficient.

 

Picture4a

Picture4b

Figure 4: Buck-Down Converter periodic steady-state response

 

The plots for periodic steady-state response show the switch drive signal, net015 [0-12V], the output of the Switch, Switcher Output [-0.8V-12V], the buck converter output after the LC tank, Regulated Output [4.995V-5.009V]. Plots of the transient and periodic steady-state response match if overlayed and the average output from transient analysis and periodic steady-state analysis are consistent, 5.002V. In the next append, we will look at performing periodic small signal analysis to analyze the converters performance. If you have any questions about this append or would like more information, please let me know!

Arthur Schaldenbrand

Comments(5)

By Brian Williams on July 29, 2009
I have a current mode DC-DC converter which has two feedback loops. The only place a iprobe can be placed which breaks both loops is essentially between the comparator and pass transistor, however PSS/PSTB doesn't seem to handle breaking the loop at a purely digital spot. Is there a way around this?


By Frank Wiedmann on August 24, 2009
You could try to do a frequency sweep relative to the first harmonic. However, this does not seem to be possible for PSTB, at least not via ADE. You can still try a PAC simulation instead. Because your break point has a low output impedance and high input impedance, you can put a PAC source in series and calculate the loop gain as the (negative) ratio of the PAC amplitudes on both sides.

By amir on May 31, 2012
Hi, i am trying to do a PSS simulation with a boost converter with current mode control feedback. i am  facing a lot of convergence problems. i have tried to fix the tolerances , also with tsab  but it doesnot help. Does any one has an experience in this kind of circuit

By Art3 on June 11, 2012
Amir,
               Information about your circuit, your testbench, and the simulator options that you
have tried is always useful to provide when asking for assistance with debugging. Here are
some things that I look at and have useful in the past.
1) Plot the pulse width versus time to see if the circuit really is in steady state
a. My experience is that DC-to-DC Converters need to be closer to periodic
steady-state than RF circuits such as an LNA
b. You should also check that the pulse width settles to steady state and
is not oscillating, see #4
c. Use the IC61 ViVA pulse width function to plot the pulse width vs. time
2) Replace Verilog-A standard cells with transistor level equivalents
In general Verilog-A logic gates have non-physical behavior and transistor level
gates seem to converge better
3) How ideal is the circuit?
Often early in the design process, designs are “idealized” and simplified. For a
dc-to-dc converter, simplification can cause issues.
a. For example, not including circuitry to suppress shoot thru combined with
ideal switches can cause extremely large currents in the output stage. This
behavior is non-physical and can cause convergence issues.
b. Does the testbench include the EMI filter?
A dc-to-dc converter may oscillate when supplied by an ideal power supply,
using an EMI filter will suppress the oscillations
4) Even though the circuit seems to work in transient, it maybe have issues that make it
difficult to achieve periodic steady state. For example, under certain conditions, dc-to-dc
converters may oscillate and this can cause the PSS analysis to fail.  
5) If you are using the moderate error preset, try setting the method to gear2 only
6) You did not describe what you are doing with the tolerances. My experience is
that most designers tighten the tolerances and for transient analysis that often
helps. It is also useful when performing RF analyses since IP3 measurements
require high resolution in order to distinguish distortion tones from the numerical
noise floor. However for dc-to-dc converters, setting the tolerances too tight
often over-constrains the simulator and can cause convergence issues.
For PSS analysis, there is an additional tolerance parameter that effects convergence
of the periodic steady state, steadyratio
a. Steadyratio is the tolerance parameter used to determine whether the
circuit has reached steady state or not
b. In general, if you tighten the tolerances, then you need to loosen the
steadyratio or you risk over-constraining PSS analysis
c. In general for a well behaved circuit, the default value for the steadyratio
should be produce good results
d. You might want to try using the default (moderate) or relaxed(liberal) error
preset and relax the steadyratio, for example, steadyratio=1
e. If the circuit converges, then you can take advantage of Spectre save/restart
to gradually tighten the tolerances
i. Set steadyratio=1, save the results
ii. Set steadyraio=0.1, restart with the result from steadyratio=1 and save
the results
iii. Continue until you get to convergence
7) Finally, you could always talk to your support team and they can escalate issues
to R & D for you

By Amir on January 17, 2013
Hi Art, First thanks alot for your reply. I am sorry for coming back a bit late but i have tried almost everything and now with some parameters simulations do converge but there are wrong results. Is it possible if i could paste my circuit or send you details. Thanks alot once again.

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