Cadence will present SpectreRF Noise aware PLL flow latest enhancements at the DesignCon 2009 conference, based in Santa Clara . In the paper "Noise and Jitter Analysis for PLL-Based Frequency Synthesizer", we fully describe SpectreRF flow and provide a testbench for each PLL building block, such as VCO, PFD/CP, and FD, where their voltage-domain models with noise information are extracted to capture their dominant behaviors. The models are used in the top-level PLL simulation to identify key PLL characteristics including small signal effects such as noise and jitter, large signal effects such as locking settle time, and power supply and substrate interference effects. The flow is tested on an integer-N PLL. We show that the simulation results with the flow closely match transistor-level analysis while the performance is orders of magnitude faster.
We strongly recommend to all PLL designers to attend this session as this covers the basics as well as latest features of this revolutionary approach. We would also have a Cadence booth at DesignCon 2009 conference to answer any related inquiries or questions you may have.
See you there!
Abstract can be viewed at:
Yu Zhu, Senior Engineering Manager, SpectreRF, CIC, Cadence Design Systems
Jianwei Sun, Member of Consulting Staff, Cadence Design Systems
Andrew Li, Staff Product Engineer, Cadence Design Systems
Dan Feng, Senior Architect, Cadence Design Systems
Helene Thibieroz, Staff Support Engineer, Cadence Design Systems