IC Packaging and SiP

Advances in Leadframe Packaging Lead Cadence and CDS to Collaboration

2011-06-27T14:00:00Z

One thing is certain about IC Package technology -- things change quickly. Leadframe package technology is one of the oldest, most reliable and cost effective ways to connect a die to a printed circuit board. However, until recently, it had been considered low-tech; that is only for low pin count devices, and certainly not for high frequency designs. Yes, things have changed. Leadframes now support higher pin count devices, stacked die, and creative engineers are managing high speed interconnect...(read more)

Cisco and Cadence Present Co-design Paper at DesignCon

2011-02-01T15:00:00Z

Today at DesignCon, be sure to drop by Room 203 at 11:05 and see Cisco and Cadence present a paper that embedded.com told their newsletter subscribers will “capture the essence of the presentations at the conference and the quality of the technical solutions.” EEtimes (who now runs DesignCon) chose to publish the paper as an article in mid-January in the Design section of eetimes.com . When you attend today’s session, you will hear Cisco and Cadence engineers describe the development...(read more)

Favorite Features of an IC Package Designer: Wirebonding

2010-11-08T14:00:00Z

This is the fourth in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool. While wirebond packages are nothing new, the challenges associated with package designs using wirebonds have continued to grow. Stacking die in low profile packages that can go into a number of consumer devices has become more and more common. It seems every wirebond design contains more wires with less space – not only in the X/Y direction...(read more)

Favorite Features Of An IC Package Designer: Assembly Rule Checks

2010-07-28T19:01:00Z

This is the third in a series of discussions we would like to open up regarding "favorite features" in an IC Packaging implementation design tool. As the industry continues to include larger numbers of larger die in a smaller IC package, the question of "Can this be manufactured?" rings ever louder. No one likes to have their artwork reviewed by the manufacturer and receive the news that things have to change. It only has to happen once before the Assembly Rule Checks in Cadence...(read more)

Catch A Full-Wave Summer Kickoff Webinar: CST 3D Extraction Integrated With Cadence SiP

2010-05-28T17:45:00Z

Is there anyone who does not carry a mobile communication device anymore? Sending and receiving phone calls seem to be just a minor feature on these devices nowadays. With texting, email, Wi-Fi, GPS, camera, video, image recognition software, and many more features available in our hand held devices, it really doesn’t make sense to call it a “cell phone” any more. And who among us is carrying a device that is more than two years old? Clearly this industry has done its best to make...(read more)

Favorite Features Of An IC Package Designer: Rich And Diverse Set Of Import And Export File Formats

2010-05-20T21:17:00Z

This is the second in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool. Recently on a visit to an avid user of IC Package design tools, we heard the requirement mantra of efficiency and flexibility. Many package designers are seeing their designs become more and more complex with little to no additional time in the schedule. This means they need to use whatever tricks they can to get the job done efficiently....(read more)

Favorite Features of an IC Package Designer: Flexible 3D Viewing

2010-04-28T15:00:00Z

This is the first in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool. We talk to customers all the time that are designing IC packages with stacked die. While trough-silicon-via (TSV) is the wave of the future, the vast majority today are wirebonding down to the substrate from the upper die. Depending on which tools they are using, some are unsure if the wires have proper clearance. Many throw it over the wall to the process...(read more)

APD and SiP Layout 16.3 - Virtual-ly Amazing

2009-12-04T21:30:00Z

On December 2, the Cadence Allegro team went live with the Cadence Allegro and OrCAD 16.3 Virtual Conference (CAO16.3). This virtual first in EDA was an amazing success with hundreds of visitors, many of whom visited the SiP and IC Packaging booth. If you missed this event as it was happening, do not be concerned. You can still register and check out the content in the booth. You will want to pay special attention to the newest product in the SiP and IC Packaging space, Cadence SiP Layout XL. Video...(read more)

Everything You Want to Know About APD / SiP 16.2 - Bill Acito Webinar on March 18

2009-03-11T15:06:00Z

(Note: Click here to view Bill Acito's webinar.)

If you caught Jerry GenPart's blog in November on Advanced Plating Bar Checks and wondered what else is new in APD 16.2, you are in luck. On Wed, March 18, Bill Acito, Product Engineer, will review the long list of new technology available in the latest release.

As an example, you'll see how the latest HDI technology in the Allegro platform is supported in APD / SiP.

And also the wirebond enhancements.

Please join us for the webinar. To register to see it live or view an archived recording (after March 18), please click here and choose the What's New in IC Packaging / SiP webinar.

We look forward to your feedback on this foray through the latest and greatest APD features.

Brad Griffin Speaks at DesignCon - Give Him a Listen!!

2009-02-05T18:00:00Z

If you were not lucky enough to be atDesignCon this week, and many of us were not! You might be interested in the streaming interviews posted on line. Click here for link.

Scroll down the video soundbites in the right hand pane, list to what Brad says is the emerging trend and focus regarding today's advanced node IC's.

Enjoy!!

Cadence SiP and IC Packaging at DesignCon

2009-01-23T17:00:00Z

Those of you attending DesignCon in February should stop by the Cadence booth to see the latest integration of PakSi-E in SiP SI. This integration not only supports signal integrity, but also there is new package power integrity technology.

We will also be showing techniques where Package-on-Package designs can be created, optimized, and analyzed.

I also hope you will drop by the Multi-Die Chip/Package Co-Design for SiP Applications Technical Panel on Tuesday afternoon. Please be sure to come up and say hello to me.

Let us know what you think of DesignCon.

3D IC or TSV: The Next Phase in Functional Density and Miniaturization

2009-01-22T18:00:00Z

It seems that almost every semiconductor company is thinking or talking about 3D-IC stacking to boost functonal density & performance, reduce design size, reduce power consumption and hopefully reduce cost. An excellent summary of the 3D-IC design and its challenges was published recently by SCD Source and written by the popular long time industry writer Richard Goering (click here to read). 3D-IC when combined with SiP could over the ultimate advantage over SOC where time to market and product life cycles are short but functionality, performance and low-cost requirements are critical. As you will read however, there are a lot of variables and decisions to overcome,including that of design tool capability!!

Need some stability in your Package Power?

2008-10-21T13:53:00Z

It is not too late to sign up for the Package Power Integrity webinar that will be presented on 10/23 11:00 PDT. Click here to register.

This webinar will give you a heads-up on new (SPB 16.2) features in the package / SiP SI tools that can be used to analyze the package power delivery network (PDN). Attendees will learn the methodology for validating power delivery by analyzing impedance of the PDN. You'll also learn the techniques for validating power stability while signals are switching.

Hope to see you there and then let us know what you thought.

CDNLive! - 10 Gbit package design paper available to conference attendees

2008-10-01T13:22:00Z

For those of you that attended CDNLive! but may have missed the presentation on multi-gigabit package design by Kevin Roselle of Bayside Design, you can review the slide presentation by using your conference login and then downloading from here . Bayside is involved in designing many high-end packages and it was a real eye opener to hear about the trials Kevin and his team have been through as they design and debug these leading edge packages while minimizing the package cost.

Kevin was nice enough to let me tag along with him and present how Cadence is addressing or planning to address many of the design challenges. I think you will find the presentation interesting, but please let us know what you think.

TSV, mainstream or niche?

2008-09-24T11:07:00Z

I'm sure many of you will have read the article in Advanced Packaging click_here where the luminaries at Georgia-Tech talk about how TSV can take us to the next level of functional integration and miniaturization. I have heard several companies (foundries and some iDM's) talking about pilot projects in this area, but will it really become prolific? Are the days of die stacks using wirebonding numbered?

My belief is that TSV will be used in very select products, CPU's or GPU's with attached memory and controller are probably the first target area. But I have heard people talk about using TSV and 3D-IC to achieve the equivalant of a mixed-signal SOC, but with none of the drawbacks.

Of course the challenges of directly integrating chips using different materials/processes and not having thermal/expansion issues has yet to be fully explored.

Another problem area that 3D-IC and TSV might have is unwanted EM coupling from one metal layer to another across the chip boundries. This necessitates that both chips would have to be designed specifically to be mated together using 3D-IC techniques.

This might mean that they can never be used in other 3D-IC applications with other chips? In that case why bother with 3D-IC, just do a single large ASIC or SOC?

If you have any thoughts, answers or comments please feel free to enlighten me and hopefully others!!!

CDNLive! Track 8 - The Place to Be!

2008-09-11T15:18:00Z

Lively presentation on IBIS-AMI modeling, multi-gigabit package design, 3D field solvers, and advance constraint management have been taking place this week at CDNLive! If you have missed it, there is still one more day where you can learn about IC-Package co-design and manufactuing aware package design. If you do miss it, I'll blog later with pointers to these presentations once they are posted.

Hope to see you today!

brad

Analog/RF chip designers don't care about the Package?

2008-08-25T07:59:00Z

So I have an observation that I would your thoughts/input on. On several occassions I have heard from our sales and AE force that in general, chip designers (layout or circuit designers) generally do not care about the IC Package their work-of-art will go into!!

Now I kinda understand that this could be true for chips that go into leadframe packages, but...for example, lets take a complex wireless radio chip design that end up in routable substrate package (BGA/LGA), now the design team surely needs to consider the package at some stage?

Do these circuits designers really ignore package effects? Do they never communicate with the package designer? not even to send them a basic footprint and pinout of the chip?

I'm hoping that some of you do care, that you need to "interface" with the package design team, and if so, how is it done today, what works, what doesn't and what makes you want to rip your hair out? So come on, let me know, let eveyone know!

How stable is your IC Package's PDN?

2008-08-21T19:05:00Z

There are three goals for a power a delivery network (PDN): sufficiency, efficiency, and stability. Simultaneous switching of Gigahertz speed signals (i.e. DDR3) has made the stability of power a pressing issue in today’s designs. The Cadence SPB 16.2 release has addressed this challenge and will make analysis of the PDN a much easier job for IC Package Designers.

An automated flow fueled by Apache’s PakSi-E 3D field solver engine, enables the efficient extraction of coupled power, ground and signal nets. The extracted models are then used in simulation to check that power and ground voltage variations caused by signals switching simultaneously are within specification.

This topic will be addressed at CDNLive! in Silicon Valley on September 9, so be sure to attend session 81CP2 - Package Design Flow for Multi-Gigabit Devices .

In the meantime, drop me a line if you have any questions or comments.

Breaking down the 'virtual' wall

2008-08-20T15:44:00Z

In the last 3-4 months I have seen, and been involved in, a flurry of discussions around driving design using manufacturing assembly data. Call it "IP" if you want -- its fashionable!! At least two world-leading assembly and test companies -- and more than a handful of leading IC companies -- have started programs to try and bring the manufacturing engineers closer to the design engineers.

The good news, for once, is that the EDA tool supplier (Cadence) and the leader in wirebond assembly equipment (Kulicke & Soffa) were already discussing how we could help designers become more manufacturing aware. The result is that in the latest release of Allegro (16.2) users now have access to a Kulicke & Soffa validated wirebond profile library that correlates to the same profiles supplied as defaults with their equipment. If you want to read more about this go here.

What I really want to hear, is what do you other designers or manufacturing engineers think? Is this a good start, what should be next? Let me know below.

For example should the manufacturing engineer be able to see the design engineers package layout in 3D in order to better understand design intent and allow for a more productive collaboration? What else?

Verifying multi-technology chips-in-a-SiP, fact or fiction?

2008-08-20T15:34:00Z

With everyone talking about System-in-Package (SiP), one challenge that often gets ignored or overlooked is: How do you go about functionally verifying mixed technology (CMOS, GaAs etc) chips that are interconnected at the package substrate level?"

If you have ever pondered this challenge, or have tried and failed, or tried and suceeded you may be interested in this article in ChipDesign Magazine.

Have a read. I have some thoughts on this but would like to hear yours first. Let me know what you think.

PakSi-E "ocho" fuels Cadence Package SI solutions

2008-07-12T13:53:00Z

In case you haven't heard, Allegro Package SI and Cadence SiP SI solutions now work with the latest and greatest version of PakSi-E (Version 8.1) as an extraction engine. Check out the announcement from CDNLive! EMEA.

http://www.apache-da.com/apache-da/Home/NewsandEvents/PressReleases/04.28.08.html

Lack of design-chain collaboration prevents SiP to go mainstream

2008-07-11T17:30:00Z

A few years back, I was considering that the lack of an integrated design solution (tool flow) was the reason that SiP design was an "expert engineering" process -- and why it was not adopted more widely despite its benefits over SoC integration for a broad range of applications and markets.

However, since the initial release of our SiP solution (http://www.cadence.com/products/sip/index.aspx) a while back, and after having worked with several customers in the adoption of the provided complete design solution, I found that design chain was the key limitation today.

Collaboration across the design chain must be facilitated because, in order to effectively design a SiP, a complex design chain of system, SoC, circuit, package, and board designers will be involved.

Traditionally, these designers have worked independently and designs have been created, simulated, implemented, and verified separately using different tools, methods, and flows, often without a single ‘system’ level circuit simulation view of the entire design.

Major issues exist when it comes to manufacturing. The backend implementation is typically done at the package foundry as it was 20 years back in the ASIC world. Things like a PDK (Process Design Kit) as in the IC world including for example DRC rules to enable the physical verification of the package layout do not exist.

This is why the majority of complex SiP solutions, where performance relevant off-chip circuitry is part of the package, are only done at IDMs successfully. IDMs do have the necessary in-house CAD support and have close relationship with the package foundry. What is your take on this?