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Build Components Quickly and Easily with Pre-Defined Escape Routing Using Cadence 16.6 IC Packaging Tools

Comments(0)Filed under: SiP Layout, package design, EDA, Allegro package design, substrate design tools, reusable tiles

When it comes to designing a dense flip-chip die - or even defining a BGA for a complex substrate - the ability to efficiently fan out the pins in the fewest possible layers is paramount. Get this wrong, and you could end up needing additional layers in your package substrate, which will cut into your profits on each and every produced component. It is safe to say that is something that we universally want to avoid!

So, how do we go about making sure the escape routing is ideally defined? How do we do this as efficiently as possible? How do we leverage design knowledge from similar components we have designed in the past? There's one simple answer to all of these questions: reusable, known-good tiles! These handy building blocks, the LEGO® of the EDA design environment, allow you to rapidly generate a complex bump or ball pattern that will be the most efficient solution possible for your needs.

It is fortunate for all users of the Cadence Allegro Package Designer and SiP Layout tools, then, that support for tiles comes built into the tools. To learn more, keep reading, and we'll walk you through creating tiles, using them, and achieving untold levels of success with your next design.

Defining Reusable Tiles Using a Spreadsheet

In order for tiles to be a good investment for your design flow, they must have a few characteristics. First, they must be easy and quick to define and change. Second, they have to be able to contain as much - or as little - pre-defined information as is appropriate for your particular design style. And, third, they are NOT to be tied to any particular cross-section, netlist, or other design IP.

Using your spreadsheet editor of choice, you can easily define a tile containing a set of pins which are tied to padstack definitions to get the pin shape (but not layer), via structure definitions that define the escape routing and vias, and pin uses and colors that define which pins are power, ground, and signal.

In the image below, we see a spreadsheet XML file that defines three tiles: a 4x2, a 3x3 "T" shape, and a 3x3 "U" shape, designed to lock together. Only the 4x2 tile definition is currently shown, as each tile is in its own worksheet.


This tile has the padstack names assigned for the pins, the pin uses for each pin, and the via structure definition (and mirroring setting to use during placement) defined. You can also see that the pins in column C are defined as the power and ground supply for this tile and are colored as such for easy identification.

What is not defined here is the pin pitch, the cross-section layer, the tile orientation (though we have defined this one to be placed on the east side of a component by default), or the signal nets. This information will be assigned on-the-fly as we build our component.

Using Tiles to Define a Bump Pattern for a Flip-Chip

These tiles, once defined, are used through the Allegro Package Designer and SiP Layout tools' Symbol Edit application mode. Using this app mode's "add pin" ability, you can add patterns of pins based on spreadsheet definitions. While this feature is presently in beta as more feedback is gathered from you, our design community, it is fully supported. Turn it on by setting the "symed_add_pin_pattern_beta" environment variable in your User Preferences editor.

In the add pins command, switch to the pattern definition fields. You can see these populated based on our example tile above:


What are the most interesting things to note here? Let's look at some of the options:

  • Adding pins to a user group allows you to keep this tile's pins grouped together so they can be acted on as a unit. Use the same name multiple times to build up a larger, more complicated tile from smaller component tiles.
  • Under the spreadsheet file name, pick the name of the tile from the pull-down list, and choose whether to highlight nets (like your power and ground nets) based on the cell colors in your spreadsheet file
  • Define the pin pitch for your specific tile. Whether you set the horizontal and vertical pitch, or the diagonal, is up to you.

Once you have things configured, you can see your tile on your cursor in the design canvas. Use the "snap to..." options in your RMB menu during placement to place a tile snapped exactly next to another tile boundary, reference pin, or the edge of your component.

Creating Tiles from your Existing Components

We've covered some interesting ground already. But, what if you need to make changes to these tiles and export them to a spreadsheet? Maybe new routing technologies or different bump shapes allow for tighter spacing but also require a different via structure definition. Have no fear. You don't need to manually copy your XML spreadsheet and type in every change to each of the worksheets!

Still in the symbol edit app mode, select the pins that you want to turn into a new (or updated) tile. If you defined individual groups for the tiles, you can turn on groups in your find filter and select one of those groups. RMB on the selected pins and, from the menu that comes up, pick the "Write Symbol Spreadsheet" entry. You'll be able to export just the selected pins into a new spreadsheet file (or append it to an existing one).  

How Can This Tool Improve Your Design Flow - Or Itself Be Improved?

Today, we hope we've given you some ideas for how to creatively leverage capabilities in the 16.6 SiP Layout and Allegro Package Designer substrate design tools you may not have even realized were there. Here at Cadence, there is a strong belief that everything can be improved upon. Share your ideas with us on how this flow can be extended to take your particular flow to the next level. With the next release, you may well see those suggestions become reality!


Jeff Gallagher


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