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Cadence Sigrity Full-Wave 3D Field Solver Technology Highlighted at CDNLive SV 2014

Comments(0)Filed under: signal integrity, power integrity, IC package design, 3DEM, full wave 3D field solver, single and multi-fabric design

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. For the complete two day agenda, click here.

Track 6, the IC Packaging/SI, PI featured customer papers on co-design as well as signal and power integrity. With the challenges of faster speeds, denser designs, and lower product costs permeating the electronics industry, it is easy to understand why there was an emphasis on 3D full-wave field solvers being utilized in PCB and IC Packaging design and analysis flows.

Cadence® Sigrity® PowerSI 3D EM Full-Wave Extraction Option (3DEM) was featured as a critical part of the design flow in two user papers and also discussed in the Cadence "how-to" paper where we discussed partitioning techniques for single and multi-fabric design challenges.

The first user paper highlighting 3DEM was delivered by Dan Lambalot of Bayside Design where he discussed the methodology used to create a wirebond package that supports 8Gbps data transfers. A number of design techniques were discussed (short wirebond wires, shielding, etc.) and 3DEM was used throughout to verify that the techniques would yield the desired results. To review the Bayside Design paper, click the image below.

 CDNLive 2014 Bayside slide


Another user paper highlighting 3DEM was delivered by BP Wong of Lattice Semiconductor. BP discussed the challenge of designing high-speed SerDes channels in IC Packages at Lattice, where real estate runs at a premium. He compared the design challenge to landing a fighter jet on an aircraft carrier in rough seas at night. A tool used by pilots dubbed as a "meatball" aids in determining the right approach angle. In BP's case, 3DEM was the tool that aided Lattice in how to trade off differential impedance and common mode impedance to meet critical design goals. For the pilot or for the package designer, BP made the case that the tool itself is only a means to the end. Expertise is required to get a successful result. To review and download the Lattice Semiconductor paper, click the image below.

 CDNLive 2014 Lattice paper


Concluding the two day event, Cadence Product Engineer, Brad Brim gave us an excellent presentation on how to "divide and conquer" to get the most out of the full-wave 3DEM technology. Also included in Brad's presentation were many tips and tricks on how to successfully extract coupled signal, power, and ground; how to manage multi-fabric simulations; and why it is unusual to have coupling between fabrics. Brad's presentation can be viewed here: 

CDNLive 2014 BB slide 

So, CDNLive SV 2014 is behind us, but there will be many more CDNLive events around the globe as the 2014 continues. If you did not make it to CDNLive SV 2014, we hope you can make it to a future CDNLive event.

Please tell us about any of your CDNLive experiences.




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