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Take Your Via Structures from Ordinary to Exceptional with 16.6 IC Packaging Advanced Commands

Comments(0)Filed under: IC Package Physical layout and co-design, Analog and RF SiP design, IC Packaging & SiP design, SiP, APD, wirebonds, wirebonding, IC packaging, APD 16.6, packaging, Allegro Package Designer, SiP Layout, 16.6, IC packaging documentation, APR, early adopter, IC Packaging and SiP Design, IC package design, BGA

Via structures—those reusable patterns of conductor clines and vias designers rely on to maximize their productivity—have a long-standing place in the robust escape routing feature set in the Cadence IC Packaging Tools.

Many of us use only the basic capabilities in the via structures repertoire, though, to create structures in the current drawing and replicate them across a pattern of pins.  Today, we'll look beyond those basics to see how a crafty package designer can really save time and energy while reducing potential errors. Take a step into the future and read on to learn more!

Converting Sets of Basic Vias to Realistic, More Complex Via Structures

There are many reasons that you may wish to hold off on using via structures until later in the flow. Most auto-routers, for instance, do not support placement of via structures during routing. Similarly, you may not know how many layers will be needed in the final substrate design until you've finished doing some preliminary routing or received the final ECO of the die pin layout and BGA ball assignments.

Whatever the reason, a handy flow to keep your design work simple while still being able to quickly optimize to the final solution with complex via structures between layers is to convert from seed vias into the final structures.

As an example, consider the desire to use the auto router for the initial routing, with via structures for the inter-layer connectivity. Start by selecting your via structure definitions. Based on these, create simple, single via padstacks with pads the same size on each layer as the extents of all the elements that will form the final structure (vias, clines, etc.). The pad will ensure that adequate clearance is maintained between the detailed via structure.

After adding these via pad definitions into the design and into the appropriate via lists in constraint manager, use the auto router of your choice—the brand new Advanced Package Router, available now in 16.6, for instance—to do the actual detailed routing. If the router is not able to get to 100% completion, or you need to make any minute adjustments, you can do so with the rich set of interactive routing commands.

Once the routing is completed to your satisfaction, start up the Route -> Via Structure -> Replace Via with Via Structure ("replace via with via structure") command.  If you haven't used this command before, you can enable it from the IC_Packaging/Early_Adopter folder in the User Preferences. From the command, pick your placeholder via and the final via structure and do a global replacement. Instantly, you've converted your design to the final via stacks.

And, best of all, you can always put them right back to the temporary vias if you need to run the auto-router or interactive routing again for any reason! How's that for failsafe?

Editing a Placed Via Structure and Applying Those Changes to All Instances

Just as you might want to delay the injection of the final via structures until later in the design, you might also need to make changes to existing via structures because of a change in the substrate parameters. Perhaps you receive a notice that the die needs an optical shrink applied, or that the scribe dimensions weren't included in the definition. These can have a dramatic impact on your routing, depending on how far along you are.

This time, let's assume that a 10% optical shrink is to be applied to the die, which can be done quite easily by importing the source die text file again and replacing the original placed die component. And, with the die replace functionality, all the clines and vias connecting to the pins will automatically move/stretch to the pin's new location.

Unfortunately, this can result in changes to the via structure definition or require that you make changes to the locations of vias and cline vertices in the structure to achieve DRC-free escape routing from under the die. If you've already used via structures for your pin escapes, fear not! You only need to modify a single instance. Change via locations, cline widths, routing bends, and whatever else might be necessary to escape that single pin properly. When you are finished, run the Route -> Via Structure -> Redefine ("redefine via structure") command. Again, if you haven't enabled this command, you can do so in the IC_Packaging/Early_Adopter folder of your User Preferences.

With this command, pick the instance of the structure that you've updated to compensate for the die shrink. The via structure definition will be updated to match the changes made at the instance level, and you have the option of automatically updating all the other instances to match these changes. In a single step, you've updated all the escape routing for hundreds of pins on your die all at once. What could be easier? Should you need to save this modified definition to disk, you can always write out an XML file for the new definition using the Route -> Via Structure -> Add.. ("add via structure") command's export feature, too. So you can update all your other designs just as easily with the batch replace via structure command.

Use Via Structures for Your Bond Finger Routing Stubs

It might be that you associate via structures with escape routing from a complex flip-chip (or offset via patterns from your BGA pads up to internal routing layers). But, don't be so quick to ignore your wire bond designs. Via structures definitely have an application here, too!

The wire bond toolset allows you to define escape distances and an optional via to be placed at the end of that stub. This is perfect for simple escapes or for single-layer packages. But, if you need a more complicated pattern that has multiple segments in the cline or continues the escape on internal substrate layers, consider using via structures instead.

With a regular escape, as you push and shove your bond fingers, only the first segment (and optionally the via at the end) will move with the bond finger, stretching to maintain connectivity with the rest of the route. By using a via structure instead, the entire structure will move along with the finger as it moves. This gives you control of the where stretches will occur in the routing to compensate for bond finger adjustments. 

Have an Idea for Making Via Structures More Useful than Ever?

We've covered three advanced concepts here. But there are as many ways to leverage via structures in your design flow as there are package designers. Do you use these design elements in a way you want others to know about? Or, do you have an idea for an enhancement that would make them more useful to you and the rest of the design community? Drop us a line and let us know! We'll be happy to help get your suggestions heard—whether it's by your fellow designers or the Cadence IC Packaging engineering team.

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