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Bending a Few IC Package Design Rules – With Confidence

Comments(0)Filed under: SiP, APD, IC packaging, Allegro Sigrity SI base, IC Packaging and SiP Design, PCB, physical layout design, XtractIM, PowerDC, package design rules, PowerSI, IC package design

Somewhere out there is an IC package designer who has been given design guidelines and cannot possibly meet the maximum layer constraints. You probably know this guy or gal (let's call her a gal). What is she supposed to do? Should she increase the number of layers and keep on tracking with the design guidelines? Probably not. More layers means more cost, and the typical package designer will not have that kind of authority.

So, the fall back will be to break a few of the guidelines. But which ones? Do we call in the experts and ask which of these design strategies imposes the least risk? If the experts are available, that would be a good approach. But if the experts are busy (and they always are) any choice she makes on her own may feel like a bad choice. But, what if she has a tool that allows her to assess the risk associated with breaking those rules? Wouldn't it be nice to have that assessment capability available at her fingertips?

While IC companies typically have separate teams for physical design and electrical analysis, Cadence now provides a design and analysis environment that allows exchanging information between the teams. In addition, the integrated design and analysis environment lets the design team use a few of the easier features in the analysis tools so that our IC Package designer can make an educated guess as to which strategy will impose the least risk on her design.

On the flip side, the analysis experts can choose to play what-if games with the layout to see the effects that physical edits to the design have on the electrical performance. This integrated environment is available in the Allegro Sigrity Integration (ASI) 16.6 release and streamlines the flow from Allegro Package Designer (APD) / SiP Layout designs to Sigrity's electrical analysis tools, such as XtractIM.

The following video demonstrates the IC package assessment capability in ASI 16.6. If video fails to open, click here.


With an easy to generate electrical assessment report of first-order accuracy, along with cross-probing functionality between the layout and the assessment report, our IC package designer will be able to easily assess her package design based upon the electrical specification provided by analysis team and devise a strategy where a few guidelines can be broken, but the electrical integrity of the design is within spec. And as you saw from the video above, the knowledge required to generate that assessment report is pretty minimal. All the set up information is physical dimensions familiar to our package designer such as solder ball/ C4 bump profile parameter, package type, and selected nets. And to make things easier, all the required setup data is made available to her in a step by step workflow.

This flow provides IC Package designers a nice opportunity to expand their contribution beyond pure physical design to valuable electrical design assessment. This is sure to increase her value to the overall team as well as reduce the design cycle time.

Let us know your experiences with the XtractIM design assessment feature and the integration to APD and SiP Layout.

Team Allegro

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