In version 16.5 of the Cadence IC package layout tools, we introduced embedded discrete component support. With the 16.6 release, that support has been extended even further. You are now able to define both manual and automatically-managed open cavities in which you can place your dies and die stacks in the SiP Layout tool, while Allegro Package Designer (APD) provides you with manual open cavity creation.
If you design substrates with one or more open cavities, be they laminate, ceramic, or even leadframe packages, 16.6 is the release you definitely want to pick up and try! To learn more about just how easy it is to create and modify your cavities, in addition to how they are integrated into all aspects of your design flow, read on!Defining Automatic Cavities in the SiP Layout Die Stack Editor
When you have dies that need to be placed into an open cavity of your package substrate, there's no easier tool for doing so than SiP Layout XL. Once you bring your die in, run the die stack editor command.
In 16.6, you have all new controls for specifying the layer that the stack sits on (based on which the tool can compute the depth of the cavity for you). You can also control the clearance from the die stack's extents to the edge of the cavity. For stadium style cavities with exposed bond fingers, setting an expansion value gives you just the right stadium shelf exposure on each new layer of the design.
Best of all, if you modify your stack or any of the dies, spacers, or interposers in it, SiP Layout will automatically adjust the cavity outline to maintain your settings. So, you don't need to give a second thought to adjusting the thickness of a dielectric layer, getting an ECO for a die that includes a size change, or even moving the entire die stack to a new position on the substrate. Your cavities will dynamically compensate for all these changes and more!Wire Bonding to Fingers in Cavities
Not only can you place dies and die stacks into cavities and have those cavities automatically adjust when the stack changes size; you can also bond to fingers exposed on internal layers of the substrate in a stadium style cavity.
All you need to do to start bonding to these cavity-exposed bond fingers is to set the wire bond global setting for finger placement in cavities, as you can see in the image here:
Once you've done that, the system will allow you to define fingers on internal substrate layers, bond to them, and push/shove them. Not only that, you get the full suite of Assembly DRC checks to ensure proper clearances between fingers and cavity edges, too.
Seeing Your Cavities in 3D
Now that you've bonded your cavity-mounted die to fingers on an internal layer, you probably want to admire your handiwork (and verify wire to die and cavity edge clearances in true 3D). Do this by bringing up the 3D Viewer with dielectrics displayed and you'll see not just your die placed at its proper height - you'll see the exact outline of the cavity, as well:
Need to DRC against the cavity outline? No problem! You can define 3D DRC rules for one (or all) of your wire profiles versus the cavity edge and see right away if you have any problems.
Being able to design, view, verify, and simulate your package substrate with the actual cavity shapes cut from the substrate layers gives you even more design options for your next package. So, pick up a copy of 16.6 and try it out for yourself!
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