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Cisco and Cadence Present Co-design Paper at DesignCon

Comments(0)Filed under: Digital SiP design, IC Packaging & SiP design, SiP, IC Package, Physical layout and co-design, Cisco, DesignCon

Today at DesignCon, be sure to drop by Room 203 at 11:05 and see Cisco and Cadence present a paper that embedded.com told their newsletter subscribers will “capture the essence of the presentations at the conference and the quality of the technical solutions.” EEtimes (who now runs DesignCon) chose to publish the paper as an article in mid-January in the Design section of eetimes.com.

When you attend today’s session, you will hear Cisco and Cadence engineers describe the development of an IC, package and PCB in a concurrent design methodology that drives a chip´s I/O plan, and how they collaborated to simplify the routability of the PCB interconnect paths for better signal quality as seen in the slide below.


Optimize Interconnect with co-design


The paper will also discuss future imporvements that Cisco and Cadence agree should be implemented.  Attending this paper will allow you hear about the savings Cisco experienced using this methodology as well as let you add your suggestions about methodology improvements.

If you are able to attend the paper, or if you have thoughts about chip-package-board co-design, let us see your comments here.







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