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Catch A Full-Wave Summer Kickoff Webinar: CST 3D Extraction Integrated With Cadence SiP

Comments(0)Filed under: SI analysis and modeling, Digital SiP design, Analog and RF SiP design, SiP, webinar, APD, SPB16.3, Allegro 16.3

Is there anyone who does not carry a mobile communication device anymore?  Sending and receiving phone calls seem to be just a minor feature on these devices nowadays.  With texting, email, Wi-Fi, GPS, camera, video, image recognition software, and many more features available in our hand held devices, it really doesn’t make sense to call it a “cell phone” any more.  And who among us is carrying a device that is more than two years old?  Clearly this industry has done its best to make sure that last year’s model is a dinosaur.

Inside that mobile device you carry around is a printed circuit board.  And on that PCB are a number of components that contain multiple pieces of silicon.  Designing and producing each individual piece of that silicon is somewhat of a modern miracle in itself, but these days, the task of connecting each piece of the silicon together has become more challenging than solving a Rubik’s cube.

The 3D nature of connecting up all this silicon makes the modeling much more challenging then it was when things were much more  two dimensional.


Multiple devices migrate to single device with stacked die


Unfortunately, 3D modeling has traditionally been delegated to an “expert”.  However, with such a large percentage of semiconductor devices targeted for handheld devices, and with those devices having a relatively short product life cycle, it is clear that the supply of experts available will not meet the demand for 3D modeling.  This design challenge is recognized by both implementation and modeling tool suppliers alike.  As an example of that, Cadence, a leader in package design and implementation has been working closely with CST, a leader in package model extraction, to provide an integrated, easy to use flow that puts 3D modeling and simulation into the hands of a significantly larger percentage of the design community.

The integration of Cadence SiP SI and CST’s 3D full-wave field solver will be demonstrated in a webinar on June 23.  Please click here to register for this webinar and be the first on your design team to learn how to break the “expert barrier” with respect to 3D full wave modeling of complex multi-die packages.

Let us hear your feedback on this important webinar.



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