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Cadence SiP and IC Packaging at DesignCon

Comments(0)Filed under: IC Package Physical layout and co-design, Digital SiP design, IC Packaging & SiP design, TSV, 3D-IC, Digital SiP desgn

Those of you attending DesignCon in February should stop by the Cadence booth to see the latest integration of PakSi-E in SiP SI.  This integration not only supports signal integrity, but also there is new package power integrity technology.

 

We will also be showing techniques where Package-on-Package designs can be created, optimized, and analyzed.

 

I also hope you will drop by the Multi-Die Chip/Package Co-Design for SiP Applications Technical Panel on Tuesday afternoon.  Please be sure to come up and say hello to me.

 

Let us know what you think of DesignCon.

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