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3D IC or TSV: The Next Phase in Functional Density and Miniaturization

Comments(0)Filed under: IC Package Physical layout and co-design, Analog and RF SiP design, IC Packaging & SiP design, TSVi, Digital SiP desgn

It seems that almost every semiconductor company is thinking or talking about 3D-IC stacking to boost functonal density & performance, reduce design size, reduce power consumption and hopefully reduce cost. An excellent summary of the 3D-IC design and its challenges was published recently by SCD Source and written by the popular long time industry writer Richard Goering (click here to read).  3D-IC when combined with SiP could over the ultimate advantage over SOC where time to market and product life cycles are short but functionality, performance and low-cost requirements are critical.  As you will read however, there are a lot of variables and decisions to overcome,including that of design tool capability!!

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