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TSV, mainstream or niche?

Comments(0)Filed under: IC Package Physical layout and co-design, Digital SiP design, Analog and RF SiP design, IC Packaging & SiP design, IDMs, TSV, 3D-IC

I'm sure many of you will have read the article in Advanced Packaging click_here where the luminaries at Georgia-Tech talk about how TSV can take us to the next level of functional integration and miniaturization.  I have heard several companies (foundries and some iDM's) talking about pilot projects in this area, but will it really become prolific?  Are the days of die stacks using wirebonding numbered?

My belief is that TSV will be used in very select products, CPU's or GPU's with attached memory and controller are probably the first target area.  But I have heard people talk about using TSV and 3D-IC to achieve the equivalant of a mixed-signal SOC, but with none of the drawbacks.

Of course the challenges of directly integrating chips using different materials/processes and not having thermal/expansion issues has yet to be fully explored.

Another problem area that 3D-IC and TSV might have is unwanted EM coupling from one metal layer to another across the chip boundries. This necessitates that both chips would have to be designed specifically to be mated together using 3D-IC techniques.

This might mean that they can never be used in other 3D-IC applications with other chips?  In that case why bother with 3D-IC, just do a single large ASIC or SOC?

If you have any thoughts, answers or comments please feel free to enlighten me and hopefully others!!! 

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