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Breaking down the 'virtual' wall

Comments(0)Filed under: IC Packaging & SiP design, Cadence, wirebond profile library, IP, Kulicke & Soffa, Allegro 16.2

In the last 3-4 months I have seen, and been involved in, a flurry of discussions around driving design using manufacturing assembly data. Call it "IP" if you want -- its fashionable!! At least two world-leading assembly and test companies -- and more than a handful of leading IC companies -- have started programs to try and bring the manufacturing engineers closer to the design engineers.

The good news, for once, is that the EDA tool supplier (Cadence) and the leader in wirebond assembly equipment (Kulicke & Soffa) were already discussing how we could help designers become more manufacturing aware.  The result is that in the latest release of Allegro (16.2) users now have access to a Kulicke & Soffa validated wirebond profile library that correlates to the same profiles supplied as defaults with their equipment.  If you want to read more about this go here.

What I really want to hear, is what do you other designers or manufacturing engineers think?  Is this a good start, what should be next? Let me know below.

For example should the manufacturing engineer be able to see the design engineers package layout in 3D in order to better understand design intent and allow for a more productive collaboration? What else?


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