What's Good About Allegro GRE 2 Point Flow? It’s in the 16.5 Release!
By Gerald "Jerry" Grzenia
on May 15, 2012
The 16.5 Allegro Global Route Environment (GRE) has been enhanced by what we call a 2 Point Flow . These flows provide the benefit of both a guided flow and the simplicity of a default flow. The 2 Point Flow: Provides the benefits of a default flow -...
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Filed under: PCB Layout and routing, PCB design, Allegro PCB Editor, Allegro, PCB Editor, PCB, layout, GRE, global route, design, routing, High Speed, SPB16.5, Allegro 16.5, bundle compression, disabiling bundle compression, interconnects, 2 point flow
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What's Good About Allegro PCB Router HDI Capabilities? 16.5 Has a Few New Enhancements!
By Gerald "Jerry" Grzenia
on May 8, 2012
More high-density interconnect (HDI) improvements including the tuning of the auto-router (Allegro PCB Router - SPECCTRA) to use the via patterns, alignment of via list priority with Allegro PCB Editor, and creation and removal of anti-acid bars are available...
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Filed under: PCB Layout and routing, PCB design, High-Density Interconnect, HDI, Allegro, via, microvia, PCB Editor, PCB, layout, design, routing, SPB16.5, Allegro 16.5, via tangency, interconnects, inset vias, via rules, vias, via patterns
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Free PCB Signal Integrity Education from Robert Hanson Continues at Cadence in Austin
By Team Allegro
on May 8, 2012
Over fifty PCB enthusiasts ascended upon the Cadence campus in Austin, Texas last month where they were greeted by world renowned signal integrity educator Robert Hanson. Robert spent two full days taking them from the basics of transmission line theory...
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Filed under: PCB design, PDN, DDR3, IBIS-AMI, Allegro, SI, PCB, PCB SI, DDR2, PCB Signal integrity, "PCB SI", "PCB PI", "Power Delivery Network", Power Delivery Network, PCB PI, PCI Express, PCB power integrity, Allegro 16.5, Allegro PCB SI, signal integrity, Robert Hanson, Austin, transmission line
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What's Good About Allegro Via Patterns During Group Routing? See for Yourself in 16.5!
By Gerald "Jerry" Grzenia
on April 30, 2012
New to the 16.5 release of Allegro PCB Editor is the ability to establish via patterns during group routing. Group Routing Review The Allegro PCB Editor supports interactive group routing. Interactive group routing is the routing of more than one net...
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Filed under: PCB Layout and routing, PCB design, SPB, Differential Pair Support, Allegro PCB Editor, High-Density Interconnect, HDI, Allegro, via, PCB Editor, PCB, layer stacks, layout, PCB Capture, "PCB design", global route, design, routing, differential pairs, diff pairs, blind vias, buried vias, SPB16.5, Allegro 16.5, inset vias, via rules, staggered vias, vias, group routing, via patterns
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What's Good About OrCAD Capture’s Find Result Report? Look to SPB16.5 and See!
By Gerald "Jerry" Grzenia
on April 23, 2012
The OrCAD Capture 16.5 release now has a method to generate a report (in CSV or HTML format) for the results from the Find command. Read on for more details… After you execute the Find command on a design, you can generate a report (in CSV or HTML...
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Filed under: PCB design, SPB, Capture CIS, OrCAD Capture, OrCAD, Schematic, Capture-CIS, PCB, Design Entry, Allegro Design Entry, Design Entry CIS, PCB Capture, "capture CIS", design, SPB16.5, Allegro 16.5, OrCAD Capture Marketplace, Find result, OrCAD reports, Find command, Capture
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What's Good About ADW’s Generic Models? Check out the 16.5 Release and See!
By Gerald "Jerry" Grzenia
on April 19, 2012
The 16.5 release of Allegro Design Workbench ( ADW ) provides support for generic models. As you’ve seen in prior releases, ADW supports the typical Cadence SPB front-to-back models – symbols, footprints, etc. Now, we offer generic model support...
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Filed under: Library and design data management, PCB design, Allegro, Librarians, Allegro Design Workbench, PCB, Library flow, ADW, "PCB design", Library, design, design data management, SPB16.5, Allegro 16.5, generic models
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What's Good About Selection Filters in DEHDL? The Secret's in the 16.5 Release!
By Gerald "Jerry" Grzenia
on April 4, 2012
In the 16.5 release of Design Entry HDL (DEHDL) -- Cadence Online Support access -- the Selection Filter helps the user select one or more type of objects in the schematic. This makes it easier to perform operations like aligning objects, distributing...
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Filed under: PCB design, Design Entry HDL, ConceptHDL, DEHDL, Allegro, Schematic, PCB, Design Entry, PCB Capture, design, SPB16.5, Allegro 16.5, 16.5, property changes, selection filters
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What's Good About PCB SI Signal Integrity Bus Analysis? Allegro 16.5 Has a Few New Enhancements!
By Gerald "Jerry" Grzenia
on March 27, 2012
Address Bus Topology Support Part of the setup for Bus Analysis in Allegro PCB SI (for Cadence Online Support access click here ) is to indicate the strobe or clock net that is to be associated with each bit of the bus being simulated. This process is...
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Filed under: PCB Signal and power integrity, PCB design, SPB, Differential Pair Support, Allegro, SI, Signal Intregrity, PCB, SigXP UI, PCB SI, SI analysis and modeling, differential pairs, diff pairs, PCB Signal integrity, "PCB SI", SPB16.5, Allegro 16.5, Allegro PCB SI, signal integrity, SI bus analysis
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What's Good About APD’s Symbol Editor App Mode? You’ll Need the 16.5 Release to See!
By Gerald "Jerry" Grzenia
on March 20, 2012
In an IC package design, it is common for the designer to customize the BGA component, or even the die components (if they are still subject to changes by the IC owner) in order to optimize the package substrate for cost and efficiency. In order to do...
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Filed under: SPB, Allegro PCB Editor, Allegro, advanced package designer, IC Packaging and SiP Design, IC Packaging, PCB, design, SPB16.5, Allegro 16.5, packaging, Allegro Package Designer, IC/package co-design, I/O, application mode, symbol editor
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What's Good About Allegro GRE Embedded Component Support? It’s in the 16.5 Release!
By Gerald "Jerry" Grzenia
on March 13, 2012
Just a quick post today … The Allegro Global Route Environment ( GRE ) has been enhanced in the 16.5 release to support embedded components. To expand Allegro's usability in the High Density Interconnect (HDI) environment, GRE has been enhanced...
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Filed under: PCB Layout and routing, PCB design, SPB, Allegro PCB Editor, High-Density Interconnect, HDI, Allegro, PCB Editor, PCB, layer stacks, layout, GRE, global route, design, routing, High Speed, SPB16.5, Allegro 16.5, embedded components
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