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Optimize Your PCB Decoupling Capacitors and Remain a Person of Integrity

Comments(0)Filed under: PDN, Power Delivery Network, High Speed, power integrity, Allegro Sigrity, power-aware SI, OptimizePI, decap

How much integrity is too much?  If your PCB designs apply one or more decoupling capacitors (decaps) per power pin, then you may have too much integrity - power integrity, that is. Your designs are also more expensive than necessary and your decap mounting structures have vias in areas that could be better applied for signal routing.  If you reduce the number of decaps, will you have less integrity?  Will your PCB's Power Delivery Network (PDN) performance (and your performance as a designer) be challenged?

Successful selection of the type and quantity of decaps and their placement locations depend on many factors.  Included in the factors are: device switching current, target impedance profiles, capacitance and inductance (ESL) of the decaps, mounting inductance of each decap and device, and PDN inductance between device and decap.  Even with the availability of detailed simulation tools to verify PDN performance, it is often not clear how to make decap implementation tradeoffs.  Pre-layout decisions tend to add more decaps than truly needed. Selection and placement is often based on experience and "best practices".  And while it is easier to remove extra decaps than to add more during post-layout verification, over-design not only adds the cost of unneeded decaps, but may unnecessarily force use of extra PCB layers due to blocked routing channels that need not be blocked.

Cadence Sigrity OptimizePI provides an analytical basis upon which to make decisions regarding PDN design tradeoffs.  Pre-layout guidance is provided for decap types and how many should be placed on the top/bottom of the design and under the devices. This helps to dramatically reduce over-design at an early stage in the design flow, where it can yield the greatest benefit to the overall design.  Post-layout analysis considers thousands of design alternatives in a completely automated manner and provides a short list of optimal decap schemes from which to select the most appropriate tradeoff for your design. PDN performance is maximized while cost, area, and emissions are simultaneously minimized.  Even for designs that have undergone pre-layout analysis, it is typical to reduce decap cost by 15% while maintaining or improving performance during post-layout optimization. For decap implementations that are over-designed from the beginning, the decap cost savings are often 50% or more with the potential for significant PDN performance improvements.

Grab a warm or frosty cold beverage and enjoy a demonstration of Cadence Sigrity OptimizePI. An 18-layer FPGA-based board is examined for which the 1.5V rail of the original design contained more than 120 decaps. This original design is observed to have impedance peaks, corresponding to high PDN noise, in the frequency range where significant energy will exist for typical switching circuits.  SPOILER ALERT: OptimizePI reduced decap cost and improved performance.

You can see from the demonstration how easily design engineers, board layout designers, and power integrity experts alike can utilize OptimizePI to provide analytical guidance for their decap implementations.

Tell us about your experiences using OptimizePI.




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