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What's Good About AMS Simulator IBIS Model Capability? It’s in the 16.6 Release!

Comments(0)Filed under: AMS simulation, SPB, Capture CIS, Capture-CIS, AMS simulator, PCB, Design Entry, AMS, IBIS, pspice, design, Grzenia, Allegro 16.6, 16.6, Cadence, Cadence Design SystemsThe 16.6 AMS Simulator now provides IBIS model simulation capability:

  • SPICE circuit generation for all IBIS versions
  • Support for V-T curves
  • Analog simulation of XNets (use Advanced Analysis tools for smoke analysis on bypass components)

Read on for more details …

The Model Editor now supports all versions of IBIS for V-T curves.

Invoke Modeled.exe.

Invoke the IBIS converter from the menu Model > IBIS Translator.

Browse to Database\IBISImport\epcs64.ibs:

Click OK to generate PSpice Model.

PSpice allows you to simulate nets with SI Model assignments in PSpice. Consider the following example circuit:

Select a design from Project Manager and invoke the library setup. Ensure the library setup is correct:

Select pins U1A.16 and U1B.11 and select RMB > Signal Integrity >Assign SI Model:

Assign any output model to the pin:

Open a TCL Command Window in Capture from the menu View > Command Window.

Type in the following TCL command to activate the IBIS netlisting -

Next, source a TCL file from your hierarchy -
source {$CDSROOT\pspice\tclscripts\IbisToPSpice\tcl\ibisnetlist.tcl}

Create a transient simulation profile Tran.

Generate the PSpice Netlist from IBIS by executing the following command -

Run the PSpice Simulation.

Plot V(Mynet).

Create new measurement:

Launch AA for Sensitivity analysis from Capture.

Import measurement.

In the AA TCL Window, enter the following command -
source {<path>\database\SimulatingSI\PspAAProcessDesign.tcl}

Run Sensitivity Analysis.

I look forward to your comments about how you’re using these new capabilities!

Jerry “GenPart” Grzenia


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